mux_pll_src_cpll_gpll_npll_npll_p 105 drivers/clk/rockchip/clk-rk3368.c PNAME(mux_pll_src_cpll_gpll_npll_npll_p) = { "cpll", "gpll", "npll", "npll" }; mux_pll_src_cpll_gpll_npll_npll_p 455 drivers/clk/rockchip/clk-rk3368.c COMPOSITE(SCLK_ISP, "sclk_isp", mux_pll_src_cpll_gpll_npll_npll_p, 0, mux_pll_src_cpll_gpll_npll_npll_p 483 drivers/clk/rockchip/clk-rk3368.c COMPOSITE(SCLK_EDP, "sclk_edp", mux_pll_src_cpll_gpll_npll_npll_p, 0, mux_pll_src_cpll_gpll_npll_npll_p 487 drivers/clk/rockchip/clk-rk3368.c COMPOSITE(SCLK_HDCP, "sclk_hdcp", mux_pll_src_cpll_gpll_npll_npll_p, 0,