mux_pll_src_3plls_p  119 drivers/clk/rockchip/clk-rk3036.c PNAME(mux_pll_src_3plls_p)	= { "apll", "dpll", "gpll" };
mux_pll_src_3plls_p  209 drivers/clk/rockchip/clk-rk3036.c 	COMPOSITE(0, "aclk_peri_src", mux_pll_src_3plls_p, 0,
mux_pll_src_3plls_p  261 drivers/clk/rockchip/clk-rk3036.c 	COMPOSITE(0, "aclk_vcodec", mux_pll_src_3plls_p, 0,
mux_pll_src_3plls_p  267 drivers/clk/rockchip/clk-rk3036.c 	COMPOSITE(0, "aclk_hvec", mux_pll_src_3plls_p, 0,
mux_pll_src_3plls_p  271 drivers/clk/rockchip/clk-rk3036.c 	COMPOSITE(0, "aclk_disp1_pre", mux_pll_src_3plls_p, 0,
mux_pll_src_3plls_p  274 drivers/clk/rockchip/clk-rk3036.c 	COMPOSITE(0, "hclk_disp_pre", mux_pll_src_3plls_p, 0,
mux_pll_src_3plls_p  277 drivers/clk/rockchip/clk-rk3036.c 	COMPOSITE(SCLK_LCDC, "dclk_lcdc", mux_pll_src_3plls_p, 0,
mux_pll_src_3plls_p  306 drivers/clk/rockchip/clk-rk3036.c 	COMPOSITE(0, "i2s_src", mux_pll_src_3plls_p, 0,
mux_pll_src_3plls_p  319 drivers/clk/rockchip/clk-rk3036.c 	COMPOSITE(0, "spdif_src", mux_pll_src_3plls_p, 0,
mux_pll_src_3plls_p  330 drivers/clk/rockchip/clk-rk3036.c 	COMPOSITE(SCLK_GPU, "sclk_gpu", mux_pll_src_3plls_p, 0,
mux_pll_src_3plls_p  334 drivers/clk/rockchip/clk-rk3036.c 	COMPOSITE(SCLK_SPI, "sclk_spi", mux_pll_src_3plls_p, 0,
mux_pll_src_3plls_p  338 drivers/clk/rockchip/clk-rk3036.c 	COMPOSITE(SCLK_NANDC, "sclk_nandc", mux_pll_src_3plls_p, 0,
mux_pll_src_3plls_p  346 drivers/clk/rockchip/clk-rk3036.c 	COMPOSITE_NOGATE(SCLK_MACPLL, "mac_pll_src", mux_pll_src_3plls_p, CLK_SET_RATE_NO_REPARENT,
mux_pll_src_3plls_p  138 drivers/clk/rockchip/clk-rk3128.c PNAME(mux_pll_src_3plls_p)	= { "cpll", "gpll", "gpll_div2" };
mux_pll_src_3plls_p  342 drivers/clk/rockchip/clk-rk3128.c 	COMPOSITE(DCLK_EBC, "dclk_ebc", mux_pll_src_3plls_p, 0,
mux_pll_src_3plls_p  356 drivers/clk/rockchip/clk-rk3128.c 	COMPOSITE(0, "i2s0_src", mux_pll_src_3plls_p, 0,
mux_pll_src_3plls_p  366 drivers/clk/rockchip/clk-rk3128.c 	COMPOSITE(0, "i2s1_src", mux_pll_src_3plls_p, 0,
mux_pll_src_3plls_p  379 drivers/clk/rockchip/clk-rk3128.c 	COMPOSITE(0, "sclk_spdif_src", mux_pll_src_3plls_p, 0,
mux_pll_src_3plls_p  403 drivers/clk/rockchip/clk-rk3128.c 	COMPOSITE(SCLK_SPI0, "sclk_spi0", mux_pll_src_3plls_p, 0,
mux_pll_src_3plls_p  432 drivers/clk/rockchip/clk-rk3128.c 	COMPOSITE(SCLK_MAC_SRC, "sclk_gmac_src", mux_pll_src_3plls_p, 0,
mux_pll_src_3plls_p  446 drivers/clk/rockchip/clk-rk3128.c 	COMPOSITE(SCLK_TSP, "sclk_tsp", mux_pll_src_3plls_p, 0,
mux_pll_src_3plls_p  450 drivers/clk/rockchip/clk-rk3128.c 	COMPOSITE(SCLK_NANDC, "sclk_nandc", mux_pll_src_3plls_p, 0,
mux_pll_src_3plls_p  141 drivers/clk/rockchip/clk-rk3228.c PNAME(mux_pll_src_3plls_p)	= { "cpll", "gpll", "hdmiphy" };
mux_pll_src_3plls_p  324 drivers/clk/rockchip/clk-rk3228.c 	COMPOSITE(SCLK_HDCP, "sclk_hdcp", mux_pll_src_3plls_p, 0,