mux_gpll_xin24m_p  146 drivers/clk/rockchip/clk-px30.c PNAME(mux_gpll_xin24m_p)		= { "gpll", "xin24m"};
mux_gpll_xin24m_p  414 drivers/clk/rockchip/clk-px30.c 	COMPOSITE(SCLK_VOPB_PWM, "clk_vopb_pwm", mux_gpll_xin24m_p, 0,
mux_gpll_xin24m_p  689 drivers/clk/rockchip/clk-px30.c 	COMPOSITE(SCLK_I2C0, "clk_i2c0", mux_gpll_xin24m_p, 0,
mux_gpll_xin24m_p  692 drivers/clk/rockchip/clk-px30.c 	COMPOSITE(SCLK_I2C1, "clk_i2c1", mux_gpll_xin24m_p, 0,
mux_gpll_xin24m_p  695 drivers/clk/rockchip/clk-px30.c 	COMPOSITE(SCLK_I2C2, "clk_i2c2", mux_gpll_xin24m_p, 0,
mux_gpll_xin24m_p  698 drivers/clk/rockchip/clk-px30.c 	COMPOSITE(SCLK_I2C3, "clk_i2c3", mux_gpll_xin24m_p, 0,
mux_gpll_xin24m_p  701 drivers/clk/rockchip/clk-px30.c 	COMPOSITE(SCLK_PWM0, "clk_pwm0", mux_gpll_xin24m_p, 0,
mux_gpll_xin24m_p  704 drivers/clk/rockchip/clk-px30.c 	COMPOSITE(SCLK_PWM1, "clk_pwm1", mux_gpll_xin24m_p, 0,
mux_gpll_xin24m_p  707 drivers/clk/rockchip/clk-px30.c 	COMPOSITE(SCLK_SPI0, "clk_spi0", mux_gpll_xin24m_p, 0,
mux_gpll_xin24m_p  710 drivers/clk/rockchip/clk-px30.c 	COMPOSITE(SCLK_SPI1, "clk_spi1", mux_gpll_xin24m_p, 0,