mux_dpll_vpll0_xin24m_p  125 drivers/clk/rockchip/clk-rk3308.c PNAME(mux_dpll_vpll0_xin24m_p)	= { "dpll", "vpll0", "xin24m" };
mux_dpll_vpll0_xin24m_p  380 drivers/clk/rockchip/clk-rk3308.c 	COMPOSITE(SCLK_I2C0, "clk_i2c0", mux_dpll_vpll0_xin24m_p, 0,
mux_dpll_vpll0_xin24m_p  383 drivers/clk/rockchip/clk-rk3308.c 	COMPOSITE(SCLK_I2C1, "clk_i2c1", mux_dpll_vpll0_xin24m_p, 0,
mux_dpll_vpll0_xin24m_p  386 drivers/clk/rockchip/clk-rk3308.c 	COMPOSITE(SCLK_I2C2, "clk_i2c2", mux_dpll_vpll0_xin24m_p, 0,
mux_dpll_vpll0_xin24m_p  389 drivers/clk/rockchip/clk-rk3308.c 	COMPOSITE(SCLK_I2C3, "clk_i2c3", mux_dpll_vpll0_xin24m_p, 0,
mux_dpll_vpll0_xin24m_p  393 drivers/clk/rockchip/clk-rk3308.c 	COMPOSITE(SCLK_PWM0, "clk_pwm0", mux_dpll_vpll0_xin24m_p, 0,
mux_dpll_vpll0_xin24m_p  396 drivers/clk/rockchip/clk-rk3308.c 	COMPOSITE(SCLK_PWM1, "clk_pwm1", mux_dpll_vpll0_xin24m_p, 0,
mux_dpll_vpll0_xin24m_p  399 drivers/clk/rockchip/clk-rk3308.c 	COMPOSITE(SCLK_PWM2, "clk_pwm2", mux_dpll_vpll0_xin24m_p, 0,
mux_dpll_vpll0_xin24m_p  403 drivers/clk/rockchip/clk-rk3308.c 	COMPOSITE(SCLK_SPI0, "clk_spi0", mux_dpll_vpll0_xin24m_p, 0,
mux_dpll_vpll0_xin24m_p  406 drivers/clk/rockchip/clk-rk3308.c 	COMPOSITE(SCLK_SPI1, "clk_spi1", mux_dpll_vpll0_xin24m_p, 0,
mux_dpll_vpll0_xin24m_p  409 drivers/clk/rockchip/clk-rk3308.c 	COMPOSITE(SCLK_SPI2, "clk_spi2", mux_dpll_vpll0_xin24m_p, 0,
mux_dpll_vpll0_xin24m_p  544 drivers/clk/rockchip/clk-rk3308.c 	COMPOSITE(SCLK_OWIRE, "clk_owire", mux_dpll_vpll0_xin24m_p, 0,