mux_dpll_vpll0_vpll1_p  126 drivers/clk/rockchip/clk-rk3308.c PNAME(mux_dpll_vpll0_vpll1_p)	= { "dpll", "vpll0", "vpll1" };
mux_dpll_vpll0_vpll1_p  315 drivers/clk/rockchip/clk-rk3308.c 	COMPOSITE_NODIV(ACLK_BUS_SRC, "clk_bus_src", mux_dpll_vpll0_vpll1_p, CLK_IGNORE_UNUSED,
mux_dpll_vpll0_vpll1_p  443 drivers/clk/rockchip/clk-rk3308.c 	COMPOSITE(SCLK_CRYPTO, "clk_crypto", mux_dpll_vpll0_vpll1_p, 0,
mux_dpll_vpll0_vpll1_p  446 drivers/clk/rockchip/clk-rk3308.c 	COMPOSITE(SCLK_CRYPTO_APK, "clk_crypto_apk", mux_dpll_vpll0_vpll1_p, 0,
mux_dpll_vpll0_vpll1_p  450 drivers/clk/rockchip/clk-rk3308.c 	COMPOSITE(0, "dclk_vop_src", mux_dpll_vpll0_vpll1_p, 0,
mux_dpll_vpll0_vpll1_p  464 drivers/clk/rockchip/clk-rk3308.c 	COMPOSITE_NODIV(ACLK_PERI_SRC, "clk_peri_src", mux_dpll_vpll0_vpll1_p, CLK_IGNORE_UNUSED,
mux_dpll_vpll0_vpll1_p  477 drivers/clk/rockchip/clk-rk3308.c 	COMPOSITE(SCLK_NANDC_DIV, "clk_nandc_div", mux_dpll_vpll0_vpll1_p, CLK_IGNORE_UNUSED,
mux_dpll_vpll0_vpll1_p  480 drivers/clk/rockchip/clk-rk3308.c 	COMPOSITE(SCLK_NANDC_DIV50, "clk_nandc_div50", mux_dpll_vpll0_vpll1_p, CLK_IGNORE_UNUSED,
mux_dpll_vpll0_vpll1_p  523 drivers/clk/rockchip/clk-rk3308.c 	COMPOSITE(SCLK_SFC, "clk_sfc", mux_dpll_vpll0_vpll1_p, 0,
mux_dpll_vpll0_vpll1_p  530 drivers/clk/rockchip/clk-rk3308.c 	COMPOSITE(SCLK_MAC_SRC, "clk_mac_src", mux_dpll_vpll0_vpll1_p, 0,
mux_dpll_vpll0_vpll1_p  564 drivers/clk/rockchip/clk-rk3308.c 	COMPOSITE(SCLK_DDRCLK, "clk_ddrphy4x_src", mux_dpll_vpll0_vpll1_p, CLK_IGNORE_UNUSED,