mux_2plls_hdmiphy_p  148 drivers/clk/rockchip/clk-rk3328.c PNAME(mux_2plls_hdmiphy_p)	= { "cpll", "gpll",
mux_2plls_hdmiphy_p  329 drivers/clk/rockchip/clk-rk3328.c 	COMPOSITE(PCLK_DDR, "pclk_ddr", mux_2plls_hdmiphy_p, 0,
mux_2plls_hdmiphy_p  348 drivers/clk/rockchip/clk-rk3328.c 	COMPOSITE(ACLK_BUS_PRE, "aclk_bus_pre", mux_2plls_hdmiphy_p, 0,
mux_2plls_hdmiphy_p  657 drivers/clk/rockchip/clk-rk3328.c 	COMPOSITE(ACLK_GMAC, "aclk_gmac", mux_2plls_hdmiphy_p, 0,