mtt_entry 105 drivers/infiniband/hw/mlx5/mem.c u64 mtt_entry = umem_dma & ODP_DMA_ADDR_MASK; mtt_entry 108 drivers/infiniband/hw/mlx5/mem.c mtt_entry |= MLX5_IB_MTT_READ; mtt_entry 110 drivers/infiniband/hw/mlx5/mem.c mtt_entry |= MLX5_IB_MTT_WRITE; mtt_entry 112 drivers/infiniband/hw/mlx5/mem.c return mtt_entry; mtt_entry 258 drivers/infiniband/hw/mthca/mthca_mr.c __be64 *mtt_entry; mtt_entry 265 drivers/infiniband/hw/mthca/mthca_mr.c mtt_entry = mailbox->buf; mtt_entry 268 drivers/infiniband/hw/mthca/mthca_mr.c mtt_entry[0] = cpu_to_be64(dev->mr_table.mtt_base + mtt_entry 271 drivers/infiniband/hw/mthca/mthca_mr.c mtt_entry[1] = 0; mtt_entry 273 drivers/infiniband/hw/mthca/mthca_mr.c mtt_entry[i + 2] = cpu_to_be64(buffer_list[i] | mtt_entry 281 drivers/infiniband/hw/mthca/mthca_mr.c mtt_entry[i + 2] = 0; mtt_entry 739 drivers/infiniband/hw/mthca/mthca_mr.c __be64 mtt_entry = cpu_to_be64(page_list[i] | mtt_entry 741 drivers/infiniband/hw/mthca/mthca_mr.c mthca_write64_raw(mtt_entry, fmr->mem.tavor.mtts + i);