mtr 37 arch/alpha/include/asm/core_titan.h titan_64 mtr; mtr 36 arch/alpha/include/asm/core_tsunami.h tsunami_64 mtr; mtr 374 arch/alpha/kernel/core_titan.c printk("%s: CSR_MTR 0x%lx\n", __func__, TITAN_cchip->mtr.csr); mtr 397 arch/alpha/kernel/core_tsunami.c printk("%s: CSR_MTR 0x%lx\n", __func__, TSUNAMI_cchip.mtr.csr); mtr 148 drivers/edac/i10nm_base.c u32 mtr, mcddrtcfg; mtr 159 drivers/edac/i10nm_base.c mtr = I10NM_GET_DIMMMTR(imc, i, j); mtr 162 drivers/edac/i10nm_base.c mtr, mcddrtcfg, imc->mc, i, j); mtr 164 drivers/edac/i10nm_base.c if (IS_DIMM_PRESENT(mtr)) mtr 165 drivers/edac/i10nm_base.c ndimms += skx_get_dimm_info(mtr, 0, 0, dimm, mtr 279 drivers/edac/i5000_edac.c #define MTR_DIMMS_PRESENT(mtr) ((mtr) & (0x1 << 8)) mtr 280 drivers/edac/i5000_edac.c #define MTR_DRAM_WIDTH(mtr) ((((mtr) >> 6) & 0x1) ? 8 : 4) mtr 281 drivers/edac/i5000_edac.c #define MTR_DRAM_BANKS(mtr) ((((mtr) >> 5) & 0x1) ? 8 : 4) mtr 282 drivers/edac/i5000_edac.c #define MTR_DRAM_BANKS_ADDR_BITS(mtr) ((MTR_DRAM_BANKS(mtr) == 8) ? 3 : 2) mtr 283 drivers/edac/i5000_edac.c #define MTR_DIMM_RANK(mtr) (((mtr) >> 4) & 0x1) mtr 284 drivers/edac/i5000_edac.c #define MTR_DIMM_RANK_ADDR_BITS(mtr) (MTR_DIMM_RANK(mtr) ? 2 : 1) mtr 285 drivers/edac/i5000_edac.c #define MTR_DIMM_ROWS(mtr) (((mtr) >> 2) & 0x3) mtr 286 drivers/edac/i5000_edac.c #define MTR_DIMM_ROWS_ADDR_BITS(mtr) (MTR_DIMM_ROWS(mtr) + 13) mtr 287 drivers/edac/i5000_edac.c #define MTR_DIMM_COLS(mtr) ((mtr) & 0x3) mtr 288 drivers/edac/i5000_edac.c #define MTR_DIMM_COLS_ADDR_BITS(mtr) (MTR_DIMM_COLS(mtr) + 10) mtr 953 drivers/edac/i5000_edac.c int mtr; mtr 956 drivers/edac/i5000_edac.c mtr = pvt->b0_mtr[slot]; mtr 958 drivers/edac/i5000_edac.c mtr = pvt->b1_mtr[slot]; mtr 960 drivers/edac/i5000_edac.c return mtr; mtr 965 drivers/edac/i5000_edac.c static void decode_mtr(int slot_row, u16 mtr) mtr 969 drivers/edac/i5000_edac.c ans = MTR_DIMMS_PRESENT(mtr); mtr 972 drivers/edac/i5000_edac.c slot_row, mtr, ans ? "" : "NOT "); mtr 976 drivers/edac/i5000_edac.c edac_dbg(2, "\t\tWIDTH: x%d\n", MTR_DRAM_WIDTH(mtr)); mtr 977 drivers/edac/i5000_edac.c edac_dbg(2, "\t\tNUMBANK: %d bank(s)\n", MTR_DRAM_BANKS(mtr)); mtr 979 drivers/edac/i5000_edac.c MTR_DIMM_RANK(mtr) ? "double" : "single"); mtr 981 drivers/edac/i5000_edac.c MTR_DIMM_ROWS(mtr) == 0 ? "8,192 - 13 rows" : mtr 982 drivers/edac/i5000_edac.c MTR_DIMM_ROWS(mtr) == 1 ? "16,384 - 14 rows" : mtr 983 drivers/edac/i5000_edac.c MTR_DIMM_ROWS(mtr) == 2 ? "32,768 - 15 rows" : mtr 986 drivers/edac/i5000_edac.c MTR_DIMM_COLS(mtr) == 0 ? "1,024 - 10 columns" : mtr 987 drivers/edac/i5000_edac.c MTR_DIMM_COLS(mtr) == 1 ? "2,048 - 11 columns" : mtr 988 drivers/edac/i5000_edac.c MTR_DIMM_COLS(mtr) == 2 ? "4,096 - 12 columns" : mtr 995 drivers/edac/i5000_edac.c int mtr; mtr 999 drivers/edac/i5000_edac.c mtr = determine_mtr(pvt, slot, channel); mtr 1000 drivers/edac/i5000_edac.c if (MTR_DIMMS_PRESENT(mtr)) { mtr 1005 drivers/edac/i5000_edac.c dinfo->dual_rank = MTR_DIMM_RANK(mtr); mtr 1009 drivers/edac/i5000_edac.c addrBits = MTR_DRAM_BANKS_ADDR_BITS(mtr); mtr 1011 drivers/edac/i5000_edac.c addrBits += MTR_DIMM_ROWS_ADDR_BITS(mtr); mtr 1013 drivers/edac/i5000_edac.c addrBits += MTR_DIMM_COLS_ADDR_BITS(mtr); mtr 1253 drivers/edac/i5000_edac.c int mtr; mtr 1273 drivers/edac/i5000_edac.c mtr = determine_mtr(pvt, slot, channel); mtr 1275 drivers/edac/i5000_edac.c if (!MTR_DIMMS_PRESENT(mtr)) mtr 1289 drivers/edac/i5000_edac.c if (MTR_DRAM_WIDTH(mtr) == 8) mtr 339 drivers/edac/i5100_edac.c } mtr[I5100_CHANNELS][I5100_MAX_RANKS_PER_CHAN]; mtr 666 drivers/edac/i5100_edac.c if (!priv->mtr[chan][chan_rank].present) mtr 671 drivers/edac/i5100_edac.c priv->mtr[chan][chan_rank].numcol + mtr 672 drivers/edac/i5100_edac.c priv->mtr[chan][chan_rank].numrow + mtr 673 drivers/edac/i5100_edac.c priv->mtr[chan][chan_rank].numbank; mtr 697 drivers/edac/i5100_edac.c priv->mtr[i][j].present = i5100_mtr_present(w); mtr 698 drivers/edac/i5100_edac.c priv->mtr[i][j].ethrottle = i5100_mtr_ethrottle(w); mtr 699 drivers/edac/i5100_edac.c priv->mtr[i][j].width = 4 + 4 * i5100_mtr_width(w); mtr 700 drivers/edac/i5100_edac.c priv->mtr[i][j].numbank = 2 + i5100_mtr_numbank(w); mtr 701 drivers/edac/i5100_edac.c priv->mtr[i][j].numrow = 13 + i5100_mtr_numrow(w); mtr 702 drivers/edac/i5100_edac.c priv->mtr[i][j].numcol = 10 + i5100_mtr_numcol(w); mtr 868 drivers/edac/i5100_edac.c dimm->dtype = (priv->mtr[chan][rank].width == 4) ? mtr 285 drivers/edac/i5400_edac.c #define MTR_DIMMS_PRESENT(mtr) ((mtr) & (1 << 10)) mtr 286 drivers/edac/i5400_edac.c #define MTR_DIMMS_ETHROTTLE(mtr) ((mtr) & (1 << 9)) mtr 287 drivers/edac/i5400_edac.c #define MTR_DRAM_WIDTH(mtr) (((mtr) & (1 << 8)) ? 8 : 4) mtr 288 drivers/edac/i5400_edac.c #define MTR_DRAM_BANKS(mtr) (((mtr) & (1 << 6)) ? 8 : 4) mtr 289 drivers/edac/i5400_edac.c #define MTR_DRAM_BANKS_ADDR_BITS(mtr) ((MTR_DRAM_BANKS(mtr) == 8) ? 3 : 2) mtr 290 drivers/edac/i5400_edac.c #define MTR_DIMM_RANK(mtr) (((mtr) >> 5) & 0x1) mtr 291 drivers/edac/i5400_edac.c #define MTR_DIMM_RANK_ADDR_BITS(mtr) (MTR_DIMM_RANK(mtr) ? 2 : 1) mtr 292 drivers/edac/i5400_edac.c #define MTR_DIMM_ROWS(mtr) (((mtr) >> 2) & 0x3) mtr 293 drivers/edac/i5400_edac.c #define MTR_DIMM_ROWS_ADDR_BITS(mtr) (MTR_DIMM_ROWS(mtr) + 13) mtr 294 drivers/edac/i5400_edac.c #define MTR_DIMM_COLS(mtr) ((mtr) & 0x3) mtr 295 drivers/edac/i5400_edac.c #define MTR_DIMM_COLS_ADDR_BITS(mtr) (MTR_DIMM_COLS(mtr) + 10) mtr 863 drivers/edac/i5400_edac.c int mtr; mtr 878 drivers/edac/i5400_edac.c mtr = pvt->b0_mtr[n]; mtr 880 drivers/edac/i5400_edac.c mtr = pvt->b1_mtr[n]; mtr 882 drivers/edac/i5400_edac.c return mtr; mtr 887 drivers/edac/i5400_edac.c static void decode_mtr(int slot_row, u16 mtr) mtr 891 drivers/edac/i5400_edac.c ans = MTR_DIMMS_PRESENT(mtr); mtr 894 drivers/edac/i5400_edac.c slot_row, mtr, ans ? "" : "NOT "); mtr 898 drivers/edac/i5400_edac.c edac_dbg(2, "\t\tWIDTH: x%d\n", MTR_DRAM_WIDTH(mtr)); mtr 901 drivers/edac/i5400_edac.c MTR_DIMMS_ETHROTTLE(mtr) ? "enabled" : "disabled"); mtr 903 drivers/edac/i5400_edac.c edac_dbg(2, "\t\tNUMBANK: %d bank(s)\n", MTR_DRAM_BANKS(mtr)); mtr 905 drivers/edac/i5400_edac.c MTR_DIMM_RANK(mtr) ? "double" : "single"); mtr 907 drivers/edac/i5400_edac.c MTR_DIMM_ROWS(mtr) == 0 ? "8,192 - 13 rows" : mtr 908 drivers/edac/i5400_edac.c MTR_DIMM_ROWS(mtr) == 1 ? "16,384 - 14 rows" : mtr 909 drivers/edac/i5400_edac.c MTR_DIMM_ROWS(mtr) == 2 ? "32,768 - 15 rows" : mtr 912 drivers/edac/i5400_edac.c MTR_DIMM_COLS(mtr) == 0 ? "1,024 - 10 columns" : mtr 913 drivers/edac/i5400_edac.c MTR_DIMM_COLS(mtr) == 1 ? "2,048 - 11 columns" : mtr 914 drivers/edac/i5400_edac.c MTR_DIMM_COLS(mtr) == 2 ? "4,096 - 12 columns" : mtr 921 drivers/edac/i5400_edac.c int mtr; mtr 925 drivers/edac/i5400_edac.c mtr = determine_mtr(pvt, dimm, channel); mtr 926 drivers/edac/i5400_edac.c if (MTR_DIMMS_PRESENT(mtr)) { mtr 933 drivers/edac/i5400_edac.c addrBits = MTR_DRAM_BANKS_ADDR_BITS(mtr); mtr 935 drivers/edac/i5400_edac.c addrBits += MTR_DIMM_ROWS_ADDR_BITS(mtr); mtr 937 drivers/edac/i5400_edac.c addrBits += MTR_DIMM_COLS_ADDR_BITS(mtr); mtr 939 drivers/edac/i5400_edac.c addrBits += MTR_DIMM_RANK(mtr); mtr 1175 drivers/edac/i5400_edac.c int mtr; mtr 1193 drivers/edac/i5400_edac.c mtr = determine_mtr(pvt, slot, channel); mtr 1196 drivers/edac/i5400_edac.c if (!MTR_DIMMS_PRESENT(mtr)) mtr 1210 drivers/edac/i5400_edac.c dimm->dtype = MTR_DRAM_WIDTH(mtr) == 8 ? mtr 1217 drivers/edac/i5400_edac.c dimm->edac_mode = MTR_DRAM_WIDTH(mtr) == 8 ? mtr 105 drivers/edac/i7300_edac.c u16 mtr[MAX_SLOTS][MAX_BRANCHES]; /* Memory Technlogy Reg */ mtr 172 drivers/edac/i7300_edac.c #define MTR_DIMMS_PRESENT(mtr) ((mtr) & (1 << 8)) mtr 173 drivers/edac/i7300_edac.c #define MTR_DIMMS_ETHROTTLE(mtr) ((mtr) & (1 << 7)) mtr 174 drivers/edac/i7300_edac.c #define MTR_DRAM_WIDTH(mtr) (((mtr) & (1 << 6)) ? 8 : 4) mtr 175 drivers/edac/i7300_edac.c #define MTR_DRAM_BANKS(mtr) (((mtr) & (1 << 5)) ? 8 : 4) mtr 176 drivers/edac/i7300_edac.c #define MTR_DIMM_RANKS(mtr) (((mtr) & (1 << 4)) ? 1 : 0) mtr 177 drivers/edac/i7300_edac.c #define MTR_DIMM_ROWS(mtr) (((mtr) >> 2) & 0x3) mtr 179 drivers/edac/i7300_edac.c #define MTR_DIMM_ROWS_ADDR_BITS(mtr) (MTR_DIMM_ROWS(mtr) + 13) mtr 180 drivers/edac/i7300_edac.c #define MTR_DIMM_COLS(mtr) ((mtr) & 0x3) mtr 181 drivers/edac/i7300_edac.c #define MTR_DIMM_COLS_ADDR_BITS(mtr) (MTR_DIMM_COLS(mtr) + 10) mtr 590 drivers/edac/i7300_edac.c int mtr, ans, addrBits, channel; mtr 594 drivers/edac/i7300_edac.c mtr = pvt->mtr[slot][branch]; mtr 595 drivers/edac/i7300_edac.c ans = MTR_DIMMS_PRESENT(mtr) ? 1 : 0; mtr 608 drivers/edac/i7300_edac.c addrBits += MTR_DIMM_ROWS_ADDR_BITS(mtr); mtr 610 drivers/edac/i7300_edac.c addrBits += MTR_DIMM_COLS_ADDR_BITS(mtr); mtr 612 drivers/edac/i7300_edac.c addrBits += MTR_DIMM_RANKS(mtr); mtr 620 drivers/edac/i7300_edac.c edac_dbg(2, "\t\tWIDTH: x%d\n", MTR_DRAM_WIDTH(mtr)); mtr 623 drivers/edac/i7300_edac.c MTR_DIMMS_ETHROTTLE(mtr) ? "enabled" : "disabled"); mtr 625 drivers/edac/i7300_edac.c edac_dbg(2, "\t\tNUMBANK: %d bank(s)\n", MTR_DRAM_BANKS(mtr)); mtr 627 drivers/edac/i7300_edac.c MTR_DIMM_RANKS(mtr) ? "double" : "single"); mtr 629 drivers/edac/i7300_edac.c MTR_DIMM_ROWS(mtr) == 0 ? "8,192 - 13 rows" : mtr 630 drivers/edac/i7300_edac.c MTR_DIMM_ROWS(mtr) == 1 ? "16,384 - 14 rows" : mtr 631 drivers/edac/i7300_edac.c MTR_DIMM_ROWS(mtr) == 2 ? "32,768 - 15 rows" : mtr 634 drivers/edac/i7300_edac.c MTR_DIMM_COLS(mtr) == 0 ? "1,024 - 10 columns" : mtr 635 drivers/edac/i7300_edac.c MTR_DIMM_COLS(mtr) == 1 ? "2,048 - 11 columns" : mtr 636 drivers/edac/i7300_edac.c MTR_DIMM_COLS(mtr) == 2 ? "4,096 - 12 columns" : mtr 657 drivers/edac/i7300_edac.c if (MTR_DRAM_WIDTH(mtr) == 8) mtr 664 drivers/edac/i7300_edac.c if (MTR_DRAM_WIDTH(mtr) == 8) { mtr 673 drivers/edac/i7300_edac.c return mtr; mtr 750 drivers/edac/i7300_edac.c int mtr; mtr 793 drivers/edac/i7300_edac.c &pvt->mtr[slot][branch]); mtr 802 drivers/edac/i7300_edac.c mtr = decode_mtr(pvt, slot, ch, branch, mtr 806 drivers/edac/i7300_edac.c if (!MTR_DIMMS_PRESENT(mtr)) mtr 213 drivers/edac/sb_edac.c #define RANK_DISABLE(mtr) GET_BITFIELD(mtr, 16, 19) mtr 214 drivers/edac/sb_edac.c #define IS_DIMM_PRESENT(mtr) GET_BITFIELD(mtr, 14, 14) mtr 215 drivers/edac/sb_edac.c #define RANK_CNT_BITS(mtr) GET_BITFIELD(mtr, 12, 13) mtr 216 drivers/edac/sb_edac.c #define RANK_WIDTH_BITS(mtr) GET_BITFIELD(mtr, 2, 4) mtr 217 drivers/edac/sb_edac.c #define COL_WIDTH_BITS(mtr) GET_BITFIELD(mtr, 0, 1) mtr 329 drivers/edac/sb_edac.c enum dev_type (*get_width)(struct sbridge_pvt *pvt, u32 mtr); mtr 689 drivers/edac/sb_edac.c static inline int numrank(enum type type, u32 mtr) mtr 691 drivers/edac/sb_edac.c int ranks = (1 << RANK_CNT_BITS(mtr)); mtr 699 drivers/edac/sb_edac.c ranks, max, (unsigned int)RANK_CNT_BITS(mtr), mtr); mtr 706 drivers/edac/sb_edac.c static inline int numrow(u32 mtr) mtr 708 drivers/edac/sb_edac.c int rows = (RANK_WIDTH_BITS(mtr) + 12); mtr 712 drivers/edac/sb_edac.c rows, (unsigned int)RANK_WIDTH_BITS(mtr), mtr); mtr 719 drivers/edac/sb_edac.c static inline int numcol(u32 mtr) mtr 721 drivers/edac/sb_edac.c int cols = (COL_WIDTH_BITS(mtr) + 10); mtr 725 drivers/edac/sb_edac.c cols, (unsigned int)COL_WIDTH_BITS(mtr), mtr); mtr 926 drivers/edac/sb_edac.c static enum dev_type knl_get_width(struct sbridge_pvt *pvt, u32 mtr) mtr 932 drivers/edac/sb_edac.c static enum dev_type sbridge_get_width(struct sbridge_pvt *pvt, u32 mtr) mtr 938 drivers/edac/sb_edac.c static enum dev_type __ibridge_get_width(u32 mtr) mtr 942 drivers/edac/sb_edac.c switch (mtr) { mtr 960 drivers/edac/sb_edac.c static enum dev_type ibridge_get_width(struct sbridge_pvt *pvt, u32 mtr) mtr 966 drivers/edac/sb_edac.c return __ibridge_get_width(GET_BITFIELD(mtr, 7, 8)); mtr 969 drivers/edac/sb_edac.c static enum dev_type broadwell_get_width(struct sbridge_pvt *pvt, u32 mtr) mtr 972 drivers/edac/sb_edac.c return __ibridge_get_width(GET_BITFIELD(mtr, 8, 9)); mtr 1608 drivers/edac/sb_edac.c u32 mtr; mtr 1626 drivers/edac/sb_edac.c knl_mtr_reg, &mtr); mtr 1629 drivers/edac/sb_edac.c mtr_regs[j], &mtr); mtr 1631 drivers/edac/sb_edac.c edac_dbg(4, "Channel #%d MTR%d = %x\n", i, j, mtr); mtr 1632 drivers/edac/sb_edac.c if (IS_DIMM_PRESENT(mtr)) { mtr 1641 drivers/edac/sb_edac.c ranks = numrank(pvt->info.type, mtr); mtr 1649 drivers/edac/sb_edac.c rows = numrow(mtr); mtr 1650 drivers/edac/sb_edac.c cols = numcol(mtr); mtr 1663 drivers/edac/sb_edac.c dimm->dtype = pvt->info.get_width(pvt, mtr); mtr 162 drivers/edac/skx_base.c u32 mtr, mcmtr, amap, mcddrtcfg; mtr 179 drivers/edac/skx_base.c 0x80 + 4 * j, &mtr); mtr 180 drivers/edac/skx_base.c if (IS_DIMM_PRESENT(mtr)) { mtr 181 drivers/edac/skx_base.c ndimms += skx_get_dimm_info(mtr, mcmtr, amap, dimm, imc, i, j); mtr 165 drivers/edac/skx_common.c static int get_width(u32 mtr) mtr 167 drivers/edac/skx_common.c switch (GET_BITFIELD(mtr, 8, 9)) { mtr 286 drivers/edac/skx_common.c int skx_get_dimm_info(u32 mtr, u32 mcmtr, u32 amap, struct dimm_info *dimm, mtr 292 drivers/edac/skx_common.c ranks = numrank(mtr); mtr 293 drivers/edac/skx_common.c rows = numrow(mtr); mtr 294 drivers/edac/skx_common.c cols = numcol(mtr); mtr 314 drivers/edac/skx_common.c dimm->dtype = get_width(mtr); mtr 129 drivers/edac/skx_common.h int skx_get_dimm_info(u32 mtr, u32 mcmtr, u32 amap, struct dimm_info *dimm, mtr 665 drivers/infiniband/hw/hns/hns_roce_device.h struct hns_roce_mtr mtr; mtr 1140 drivers/infiniband/hw/hns/hns_roce_device.h void hns_roce_mtr_init(struct hns_roce_mtr *mtr, int bt_pg_shift, mtr 1142 drivers/infiniband/hw/hns/hns_roce_device.h int hns_roce_mtr_attach(struct hns_roce_dev *hr_dev, struct hns_roce_mtr *mtr, mtr 1146 drivers/infiniband/hw/hns/hns_roce_device.h struct hns_roce_mtr *mtr); mtr 1150 drivers/infiniband/hw/hns/hns_roce_device.h int hns_roce_mtr_find(struct hns_roce_dev *hr_dev, struct hns_roce_mtr *mtr, mtr 3690 drivers/infiniband/hw/hns/hns_roce_hw_v2.c count = hns_roce_mtr_find(hr_dev, &hr_qp->mtr, mtr 3926 drivers/infiniband/hw/hns/hns_roce_hw_v2.c count = hns_roce_mtr_find(hr_dev, &hr_qp->mtr, 0, &sq_cur_blk, 1, NULL); mtr 3934 drivers/infiniband/hw/hns/hns_roce_hw_v2.c count = hns_roce_mtr_find(hr_dev, &hr_qp->mtr, mtr 4689 drivers/infiniband/hw/hns/hns_roce_hw_v2.c hns_roce_mtr_cleanup(hr_dev, &hr_qp->mtr); mtr 1564 drivers/infiniband/hw/hns/hns_roce_mr.c void hns_roce_mtr_init(struct hns_roce_mtr *mtr, int bt_pg_shift, mtr 1567 drivers/infiniband/hw/hns/hns_roce_mr.c hns_roce_hem_list_init(&mtr->hem_list, bt_pg_shift); mtr 1568 drivers/infiniband/hw/hns/hns_roce_mr.c mtr->buf_pg_shift = buf_pg_shift; mtr 1572 drivers/infiniband/hw/hns/hns_roce_mr.c struct hns_roce_mtr *mtr) mtr 1574 drivers/infiniband/hw/hns/hns_roce_mr.c hns_roce_hem_list_release(hr_dev, &mtr->hem_list); mtr 1578 drivers/infiniband/hw/hns/hns_roce_mr.c struct hns_roce_mtr *mtr, dma_addr_t *bufs, mtr 1592 drivers/infiniband/hw/hns/hns_roce_mr.c mtts = hns_roce_hem_list_find_mtt(hr_dev, &mtr->hem_list, mtr 1612 drivers/infiniband/hw/hns/hns_roce_mr.c int hns_roce_mtr_attach(struct hns_roce_dev *hr_dev, struct hns_roce_mtr *mtr, mtr 1620 drivers/infiniband/hw/hns/hns_roce_mr.c ret = hns_roce_hem_list_request(hr_dev, &mtr->hem_list, regions, mtr 1627 drivers/infiniband/hw/hns/hns_roce_mr.c ret = hns_roce_write_mtr(hr_dev, mtr, bufs[i], r); mtr 1639 drivers/infiniband/hw/hns/hns_roce_mr.c hns_roce_hem_list_release(hr_dev, &mtr->hem_list); mtr 1644 drivers/infiniband/hw/hns/hns_roce_mr.c int hns_roce_mtr_find(struct hns_roce_dev *hr_dev, struct hns_roce_mtr *mtr, mtr 1660 drivers/infiniband/hw/hns/hns_roce_mr.c addr = hns_roce_hem_list_find_mtt(hr_dev, &mtr->hem_list, mtr 1674 drivers/infiniband/hw/hns/hns_roce_mr.c *base_addr = mtr->hem_list.root_ba; mtr 909 drivers/infiniband/hw/hns/hns_roce_qp.c hns_roce_mtr_init(&hr_qp->mtr, PAGE_SHIFT + hr_qp->wqe_bt_pg_shift, mtr 911 drivers/infiniband/hw/hns/hns_roce_qp.c ret = hns_roce_mtr_attach(hr_dev, &hr_qp->mtr, buf_list, mtr 969 drivers/infiniband/hw/hns/hns_roce_qp.c hns_roce_mtr_cleanup(hr_dev, &hr_qp->mtr); mtr 8217 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, mtmp, mtr, 0x08, 30, 1);