mthd 510 drivers/gpu/drm/nouveau/dispnv50/disp.c struct nv50_disp_mthd_v1 mthd; mthd 515 drivers/gpu/drm/nouveau/dispnv50/disp.c .base.mthd.version = 1, mthd 516 drivers/gpu/drm/nouveau/dispnv50/disp.c .base.mthd.method = NV50_DISP_MTHD_V1_SOR_HDA_ELD, mthd 517 drivers/gpu/drm/nouveau/dispnv50/disp.c .base.mthd.hasht = nv_encoder->dcb->hasht, mthd 518 drivers/gpu/drm/nouveau/dispnv50/disp.c .base.mthd.hashm = (0xf0ff & nv_encoder->dcb->hashm) | mthd 49 drivers/gpu/drm/nouveau/include/nvif/cl0080.h __u64 mthd; /* NV_DEVICE_INFO_* (see below). */ mthd 21 drivers/gpu/drm/nouveau/include/nvkm/core/engine.h int (*info)(struct nvkm_engine *, u64 mthd, u64 *data); mthd 32 drivers/gpu/drm/nouveau/include/nvkm/core/object.h int (*mthd)(struct nvkm_object *, u32 mthd, void *data, u32 size); mthd 33 drivers/gpu/drm/nouveau/include/nvkm/core/object.h int (*ntfy)(struct nvkm_object *, u32 mthd, struct nvkm_event **); mthd 59 drivers/gpu/drm/nouveau/include/nvkm/core/object.h int nvkm_object_mthd(struct nvkm_object *, u32 mthd, void *data, u32 size); mthd 60 drivers/gpu/drm/nouveau/include/nvkm/core/object.h int nvkm_object_ntfy(struct nvkm_object *, u32 mthd, struct nvkm_event **); mthd 20 drivers/gpu/drm/nouveau/include/nvkm/core/subdev.h int (*info)(struct nvkm_subdev *, u64 mthd, u64 *data); mthd 13 drivers/gpu/drm/nouveau/include/nvkm/engine/sw.h bool nvkm_sw_mthd(struct nvkm_sw *sw, int chid, int subc, u32 mthd, u32 data); mthd 1195 drivers/gpu/drm/nouveau/nouveau_bo.c }, *mthd = _methods; mthd 1202 drivers/gpu/drm/nouveau/nouveau_bo.c if (mthd->engine) mthd 1210 drivers/gpu/drm/nouveau/nouveau_bo.c mthd->oclass | (mthd->engine << 16), mthd 1211 drivers/gpu/drm/nouveau/nouveau_bo.c mthd->oclass, NULL, 0, mthd 1214 drivers/gpu/drm/nouveau/nouveau_bo.c ret = mthd->init(chan, drm->ttm.copy.handle); mthd 1220 drivers/gpu/drm/nouveau/nouveau_bo.c drm->ttm.move = mthd->exec; mthd 1222 drivers/gpu/drm/nouveau/nouveau_bo.c name = mthd->name; mthd 1225 drivers/gpu/drm/nouveau/nouveau_bo.c } while ((++mthd)->exec); mthd 522 drivers/gpu/drm/nouveau/nouveau_chan.c .v.channels.mthd = NV_DEVICE_FIFO_CHANNELS, mthd 528 drivers/gpu/drm/nouveau/nouveau_chan.c if (ret || args.v.channels.mthd == NV_DEVICE_INFO_INVALID) mthd 109 drivers/gpu/drm/nouveau/nouveau_dma.h BEGIN_NV04(struct nouveau_channel *chan, int subc, int mthd, int size) mthd 111 drivers/gpu/drm/nouveau/nouveau_dma.h OUT_RING(chan, 0x00000000 | (subc << 13) | (size << 18) | mthd); mthd 115 drivers/gpu/drm/nouveau/nouveau_dma.h BEGIN_NI04(struct nouveau_channel *chan, int subc, int mthd, int size) mthd 117 drivers/gpu/drm/nouveau/nouveau_dma.h OUT_RING(chan, 0x40000000 | (subc << 13) | (size << 18) | mthd); mthd 121 drivers/gpu/drm/nouveau/nouveau_dma.h BEGIN_NVC0(struct nouveau_channel *chan, int subc, int mthd, int size) mthd 123 drivers/gpu/drm/nouveau/nouveau_dma.h OUT_RING(chan, 0x20000000 | (size << 16) | (subc << 13) | (mthd >> 2)); mthd 127 drivers/gpu/drm/nouveau/nouveau_dma.h BEGIN_NIC0(struct nouveau_channel *chan, int subc, int mthd, int size) mthd 129 drivers/gpu/drm/nouveau/nouveau_dma.h OUT_RING(chan, 0x60000000 | (size << 16) | (subc << 13) | (mthd >> 2)); mthd 133 drivers/gpu/drm/nouveau/nouveau_dma.h BEGIN_IMC0(struct nouveau_channel *chan, int subc, int mthd, u16 data) mthd 135 drivers/gpu/drm/nouveau/nouveau_dma.h OUT_RING(chan, 0x80000000 | (data << 16) | (subc << 13) | (mthd >> 2)); mthd 44 drivers/gpu/drm/nouveau/nvif/fifo.c a->v.runlists.mthd = NV_DEVICE_FIFO_RUNLISTS; mthd 46 drivers/gpu/drm/nouveau/nvif/fifo.c a->v.runlist[i].mthd = NV_DEVICE_FIFO_RUNLIST_ENGINES(i); mthd 82 drivers/gpu/drm/nouveau/nvif/fifo.c .v.engine.mthd = engine, mthd 140 drivers/gpu/drm/nouveau/nvif/object.c nvif_object_mthd(struct nvif_object *object, u32 mthd, void *data, u32 size) mthd 144 drivers/gpu/drm/nouveau/nvif/object.c struct nvif_ioctl_mthd_v0 mthd; mthd 157 drivers/gpu/drm/nouveau/nvif/object.c args->mthd.version = 0; mthd 158 drivers/gpu/drm/nouveau/nvif/object.c args->mthd.method = mthd; mthd 160 drivers/gpu/drm/nouveau/nvif/object.c memcpy(args->mthd.data, data, size); mthd 162 drivers/gpu/drm/nouveau/nvif/object.c memcpy(data, args->mthd.data, size); mthd 218 drivers/gpu/drm/nouveau/nvkm/core/client.c nvkm_client_mthd(struct nvkm_object *object, u32 mthd, void *data, u32 size) mthd 221 drivers/gpu/drm/nouveau/nvkm/core/client.c switch (mthd) { mthd 281 drivers/gpu/drm/nouveau/nvkm/core/client.c .mthd = nvkm_client_mthd, mthd 86 drivers/gpu/drm/nouveau/nvkm/core/engine.c nvkm_engine_info(struct nvkm_subdev *subdev, u64 mthd, u64 *data) mthd 91 drivers/gpu/drm/nouveau/nvkm/core/engine.c int ret = engine->func->info(engine, mthd, data); mthd 88 drivers/gpu/drm/nouveau/nvkm/core/object.c nvkm_object_mthd(struct nvkm_object *object, u32 mthd, void *data, u32 size) mthd 90 drivers/gpu/drm/nouveau/nvkm/core/object.c if (likely(object->func->mthd)) mthd 91 drivers/gpu/drm/nouveau/nvkm/core/object.c return object->func->mthd(object, mthd, data, size); mthd 96 drivers/gpu/drm/nouveau/nvkm/core/object.c nvkm_object_ntfy(struct nvkm_object *object, u32 mthd, mthd 100 drivers/gpu/drm/nouveau/nvkm/core/object.c return object->func->ntfy(object, mthd, pevent); mthd 27 drivers/gpu/drm/nouveau/nvkm/core/oproxy.c nvkm_oproxy_mthd(struct nvkm_object *object, u32 mthd, void *data, u32 size) mthd 29 drivers/gpu/drm/nouveau/nvkm/core/oproxy.c return nvkm_object_mthd(nvkm_oproxy(object)->object, mthd, data, size); mthd 33 drivers/gpu/drm/nouveau/nvkm/core/oproxy.c nvkm_oproxy_ntfy(struct nvkm_object *object, u32 mthd, mthd 36 drivers/gpu/drm/nouveau/nvkm/core/oproxy.c return nvkm_object_ntfy(nvkm_oproxy(object)->object, mthd, pevent); mthd 179 drivers/gpu/drm/nouveau/nvkm/core/oproxy.c .mthd = nvkm_oproxy_mthd, mthd 102 drivers/gpu/drm/nouveau/nvkm/core/subdev.c nvkm_subdev_info(struct nvkm_subdev *subdev, u64 mthd, u64 *data) mthd 105 drivers/gpu/drm/nouveau/nvkm/core/subdev.c return subdev->func->info(subdev, mthd, data); mthd 50 drivers/gpu/drm/nouveau/nvkm/engine/ce/gt215.c u32 mthd = (addr & 0x07ff) << 2; mthd 61 drivers/gpu/drm/nouveau/nvkm/engine/ce/gt215.c subc, mthd, data); mthd 87 drivers/gpu/drm/nouveau/nvkm/engine/cipher/g84.c u32 mthd = nvkm_rd32(device, 0x102190); mthd 100 drivers/gpu/drm/nouveau/nvkm/engine/cipher/g84.c mthd, data); mthd 170 drivers/gpu/drm/nouveau/nvkm/engine/device/ctrl.c nvkm_control_mthd(struct nvkm_object *object, u32 mthd, void *data, u32 size) mthd 173 drivers/gpu/drm/nouveau/nvkm/engine/device/ctrl.c switch (mthd) { mthd 188 drivers/gpu/drm/nouveau/nvkm/engine/device/ctrl.c .mthd = nvkm_control_mthd, mthd 43 drivers/gpu/drm/nouveau/nvkm/engine/device/user.c nvkm_udevice_info_subdev(struct nvkm_device *device, u64 mthd, u64 *data) mthd 48 drivers/gpu/drm/nouveau/nvkm/engine/device/user.c switch (mthd & NV_DEVICE_INFO_UNIT) { mthd 56 drivers/gpu/drm/nouveau/nvkm/engine/device/user.c return nvkm_subdev_info(subdev, mthd, data); mthd 64 drivers/gpu/drm/nouveau/nvkm/engine/device/user.c if (args->mthd & NV_DEVICE_INFO_UNIT) { mthd 65 drivers/gpu/drm/nouveau/nvkm/engine/device/user.c if (nvkm_udevice_info_subdev(device, args->mthd, &args->data)) mthd 66 drivers/gpu/drm/nouveau/nvkm/engine/device/user.c args->mthd = NV_DEVICE_INFO_INVALID; mthd 70 drivers/gpu/drm/nouveau/nvkm/engine/device/user.c switch (args->mthd) { mthd 97 drivers/gpu/drm/nouveau/nvkm/engine/device/user.c args->mthd = NV_DEVICE_INFO_INVALID; mthd 218 drivers/gpu/drm/nouveau/nvkm/engine/device/user.c nvkm_udevice_mthd(struct nvkm_object *object, u32 mthd, void *data, u32 size) mthd 221 drivers/gpu/drm/nouveau/nvkm/engine/device/user.c nvif_ioctl(object, "device mthd %08x\n", mthd); mthd 222 drivers/gpu/drm/nouveau/nvkm/engine/device/user.c switch (mthd) { mthd 389 drivers/gpu/drm/nouveau/nvkm/engine/device/user.c .mthd = nvkm_udevice_mthd, mthd 404 drivers/gpu/drm/nouveau/nvkm/engine/device/user.c .mthd = nvkm_udevice_mthd, mthd 28 drivers/gpu/drm/nouveau/nvkm/engine/disp/baseg84.c .mthd = 0x0000, mthd 28 drivers/gpu/drm/nouveau/nvkm/engine/disp/basegf119.c .mthd = 0x0000, mthd 78 drivers/gpu/drm/nouveau/nvkm/engine/disp/basegf119.c .mthd = 0x0020, mthd 34 drivers/gpu/drm/nouveau/nvkm/engine/disp/basenv50.c const struct nv50_disp_chan_mthd *mthd, mthd 58 drivers/gpu/drm/nouveau/nvkm/engine/disp/basenv50.c return nv50_disp_dmac_new_(func, mthd, disp, chid + head, mthd 64 drivers/gpu/drm/nouveau/nvkm/engine/disp/basenv50.c .mthd = 0x0000, mthd 89 drivers/gpu/drm/nouveau/nvkm/engine/disp/basenv50.c .mthd = 0x0400, mthd 45 drivers/gpu/drm/nouveau/nvkm/engine/disp/channv50.c for (i = 0; list->data[i].mthd; i++) { mthd 49 drivers/gpu/drm/nouveau/nvkm/engine/disp/channv50.c u32 mthd = list->data[i].mthd + (list->mthd * inst); mthd 60 drivers/gpu/drm/nouveau/nvkm/engine/disp/channv50.c mthd, prev, mods, name ? " // " : "", mthd 71 drivers/gpu/drm/nouveau/nvkm/engine/disp/channv50.c const struct nv50_disp_chan_mthd *mthd = chan->mthd; mthd 77 drivers/gpu/drm/nouveau/nvkm/engine/disp/channv50.c if (!mthd) mthd 80 drivers/gpu/drm/nouveau/nvkm/engine/disp/channv50.c for (i = 0; (list = mthd->data[i].mthd) != NULL; i++) { mthd 81 drivers/gpu/drm/nouveau/nvkm/engine/disp/channv50.c u32 base = chan->head * mthd->addr; mthd 82 drivers/gpu/drm/nouveau/nvkm/engine/disp/channv50.c for (j = 0; j < mthd->data[i].nr; j++, base += list->addr) { mthd 83 drivers/gpu/drm/nouveau/nvkm/engine/disp/channv50.c const char *cname = mthd->name; mthd 87 drivers/gpu/drm/nouveau/nvkm/engine/disp/channv50.c if (mthd->addr) { mthd 89 drivers/gpu/drm/nouveau/nvkm/engine/disp/channv50.c mthd->name, chan->chid.user); mthd 93 drivers/gpu/drm/nouveau/nvkm/engine/disp/channv50.c if (mthd->data[i].nr > 1) { mthd 95 drivers/gpu/drm/nouveau/nvkm/engine/disp/channv50.c mthd->data[i].name, j); mthd 100 drivers/gpu/drm/nouveau/nvkm/engine/disp/channv50.c nv50_disp_mthd_list(disp, debug, base, mthd->prev, mthd 339 drivers/gpu/drm/nouveau/nvkm/engine/disp/channv50.c const struct nv50_disp_chan_mthd *mthd, mthd 352 drivers/gpu/drm/nouveau/nvkm/engine/disp/channv50.c chan->mthd = mthd; mthd 11 drivers/gpu/drm/nouveau/nvkm/engine/disp/channv50.h const struct nv50_disp_chan_mthd *mthd; mthd 150 drivers/gpu/drm/nouveau/nvkm/engine/disp/channv50.h u32 mthd; mthd 153 drivers/gpu/drm/nouveau/nvkm/engine/disp/channv50.h u32 mthd; mthd 166 drivers/gpu/drm/nouveau/nvkm/engine/disp/channv50.h const struct nv50_disp_mthd_list *mthd; mthd 28 drivers/gpu/drm/nouveau/nvkm/engine/disp/coreg84.c .mthd = 0x0080, mthd 40 drivers/gpu/drm/nouveau/nvkm/engine/disp/coreg84.c .mthd = 0x0400, mthd 28 drivers/gpu/drm/nouveau/nvkm/engine/disp/coreg94.c .mthd = 0x0040, mthd 30 drivers/gpu/drm/nouveau/nvkm/engine/disp/coregf119.c .mthd = 0x0000, mthd 43 drivers/gpu/drm/nouveau/nvkm/engine/disp/coregf119.c .mthd = 0x0020, mthd 56 drivers/gpu/drm/nouveau/nvkm/engine/disp/coregf119.c .mthd = 0x0020, mthd 69 drivers/gpu/drm/nouveau/nvkm/engine/disp/coregf119.c .mthd = 0x0020, mthd 82 drivers/gpu/drm/nouveau/nvkm/engine/disp/coregf119.c .mthd = 0x0300, mthd 28 drivers/gpu/drm/nouveau/nvkm/engine/disp/coregk104.c .mthd = 0x0300, mthd 28 drivers/gpu/drm/nouveau/nvkm/engine/disp/coregv100.c .mthd = 0x0000, mthd 44 drivers/gpu/drm/nouveau/nvkm/engine/disp/coregv100.c .mthd = 0x0020, mthd 57 drivers/gpu/drm/nouveau/nvkm/engine/disp/coregv100.c .mthd = 0x0080, mthd 71 drivers/gpu/drm/nouveau/nvkm/engine/disp/coregv100.c .mthd = 0x0400, mthd 34 drivers/gpu/drm/nouveau/nvkm/engine/disp/corenv50.c const struct nv50_disp_chan_mthd *mthd, mthd 55 drivers/gpu/drm/nouveau/nvkm/engine/disp/corenv50.c return nv50_disp_dmac_new_(func, mthd, disp, chid, 0, mthd 61 drivers/gpu/drm/nouveau/nvkm/engine/disp/corenv50.c .mthd = 0x0000, mthd 74 drivers/gpu/drm/nouveau/nvkm/engine/disp/corenv50.c .mthd = 0x0080, mthd 86 drivers/gpu/drm/nouveau/nvkm/engine/disp/corenv50.c .mthd = 0x0040, mthd 96 drivers/gpu/drm/nouveau/nvkm/engine/disp/corenv50.c .mthd = 0x0040, mthd 106 drivers/gpu/drm/nouveau/nvkm/engine/disp/corenv50.c .mthd = 0x0400, mthd 35 drivers/gpu/drm/nouveau/nvkm/engine/disp/dmacnv50.c const struct nv50_disp_chan_mthd *mthd, mthd 44 drivers/gpu/drm/nouveau/nvkm/engine/disp/dmacnv50.c ret = nv50_disp_chan_new_(func, mthd, disp, chid, chid, head, oclass, mthd 96 drivers/gpu/drm/nouveau/nvkm/engine/disp/gf119.c u32 mthd = (stat & 0x00000ffc); mthd 105 drivers/gpu/drm/nouveau/nvkm/engine/disp/gf119.c mthd, data, code); mthd 108 drivers/gpu/drm/nouveau/nvkm/engine/disp/gf119.c switch (mthd) { mthd 35 drivers/gpu/drm/nouveau/nvkm/engine/disp/gp102.c u32 mthd = nvkm_rd32(device, 0x6111f0 + (chid * 12)); mthd 40 drivers/gpu/drm/nouveau/nvkm/engine/disp/gp102.c chid, (mthd & 0x0000ffc), data, mthd, unkn); mthd 43 drivers/gpu/drm/nouveau/nvkm/engine/disp/gp102.c switch (mthd & 0xffc) { mthd 103 drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c u32 mthd = (stat & 0x00000fff) << 2; mthd 112 drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c mthd, data, code); mthd 115 drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c switch (mthd) { mthd 622 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c u32 mthd = (addr & 0x00000ffc); mthd 631 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c chid, mthd, data); mthd 634 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c switch (mthd) { mthd 28 drivers/gpu/drm/nouveau/nvkm/engine/disp/ovlyg84.c .mthd = 0x0000, mthd 28 drivers/gpu/drm/nouveau/nvkm/engine/disp/ovlygf119.c .mthd = 0x0000, mthd 28 drivers/gpu/drm/nouveau/nvkm/engine/disp/ovlygk104.c .mthd = 0x0000, mthd 28 drivers/gpu/drm/nouveau/nvkm/engine/disp/ovlygt200.c .mthd = 0x0000, mthd 34 drivers/gpu/drm/nouveau/nvkm/engine/disp/ovlynv50.c const struct nv50_disp_chan_mthd *mthd, mthd 58 drivers/gpu/drm/nouveau/nvkm/engine/disp/ovlynv50.c return nv50_disp_dmac_new_(func, mthd, disp, chid + head, mthd 64 drivers/gpu/drm/nouveau/nvkm/engine/disp/ovlynv50.c .mthd = 0x0000, mthd 40 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv04.c nv04_disp_mthd(struct nvkm_object *object, u32 mthd, void *data, u32 size) mthd 53 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv04.c mthd = args->v0.method; mthd 61 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv04.c switch (mthd) { mthd 73 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv04.c .mthd = nv04_disp_mthd, mthd 37 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv50.c nv50_disp_root_mthd_(struct nvkm_object *object, u32 mthd, void *data, u32 size) mthd 50 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv50.c if (mthd != NV50_DISP_MTHD) mthd 57 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv50.c mthd = args->v0.method; mthd 65 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv50.c mthd = args->v1.method; mthd 87 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv50.c switch (mthd) { mthd 95 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv50.c switch (mthd * !!outp) { mthd 312 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv50.c .mthd = nv50_disp_root_mthd_, mthd 48 drivers/gpu/drm/nouveau/nvkm/engine/disp/wimmgv100.c const struct nv50_disp_chan_mthd *mthd, mthd 72 drivers/gpu/drm/nouveau/nvkm/engine/disp/wimmgv100.c return nv50_disp_dmac_new_(func, mthd, disp, chid + wndw, mthd 31 drivers/gpu/drm/nouveau/nvkm/engine/disp/wndwgv100.c .mthd = 0x0000, mthd 150 drivers/gpu/drm/nouveau/nvkm/engine/disp/wndwgv100.c const struct nv50_disp_chan_mthd *mthd, mthd 174 drivers/gpu/drm/nouveau/nvkm/engine/disp/wndwgv100.c return nv50_disp_dmac_new_(func, mthd, disp, chid + wndw, mthd 291 drivers/gpu/drm/nouveau/nvkm/engine/fifo/base.c nvkm_fifo_info(struct nvkm_engine *engine, u64 mthd, u64 *data) mthd 294 drivers/gpu/drm/nouveau/nvkm/engine/fifo/base.c switch (mthd) { mthd 298 drivers/gpu/drm/nouveau/nvkm/engine/fifo/base.c return fifo->func->info(fifo, mthd, data); mthd 17 drivers/gpu/drm/nouveau/nvkm/engine/fifo/changk104.h struct nvkm_memory *mthd; mthd 414 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c u32 mthd = (addr & 0x00003ffc); mthd 422 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c if (nvkm_sw_mthd(device->sw, chid, subc, mthd, data)) mthd 434 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c subc, mthd, data); mthd 694 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c u32 mthd = (addr & 0x00003ffc); mthd 702 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c if (nvkm_sw_mthd(device->sw, chid, subc, mthd, data)) mthd 716 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c subc, mthd, data); mthd 875 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c gk104_fifo_info(struct nvkm_fifo *base, u64 mthd, u64 *data) mthd 878 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c switch (mthd) { mthd 884 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c int runl = mthd - NV_DEVICE_FIFO_RUNLIST_ENGINES(0), engn; mthd 225 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c nvkm_memory_unref(&chan->mthd); mthd 134 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogv100.c u64 usermem, mthd; mthd 193 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogv100.c &chan->mthd); mthd 197 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogv100.c mthd = nvkm_memory_bar2(chan->mthd); mthd 198 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogv100.c if (mthd == ~0ULL) mthd 217 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogv100.c nvkm_wo32(chan->base.inst, 0x220, lower_32_bits(mthd)); mthd 218 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogv100.c nvkm_wo32(chan->base.inst, 0x224, upper_32_bits(mthd)); mthd 112 drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c const int mthd = (addr & 0x00001ffc); mthd 117 drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c switch (mthd) { mthd 127 drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c handled = nvkm_sw_mthd(sw, chid, subc, mthd, data); mthd 144 drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c u32 mthd, data; mthd 155 drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c mthd = nvkm_rd32(device, NV04_PFIFO_CACHE1_METHOD(ptr)); mthd 158 drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c mthd = nvkm_rd32(device, NV40_PFIFO_CACHE1_METHOD(ptr)); mthd 163 drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c !nv04_fifo_swmthd(device, chid, mthd, data)) { mthd 168 drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c (mthd >> 13) & 7, mthd & 0x1ffc, data); mthd 21 drivers/gpu/drm/nouveau/nvkm/engine/fifo/priv.h int (*info)(struct nvkm_fifo *, u64 mthd, u64 *data); mthd 1417 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c gf100_gr_mthd(gr, grctx->mthd); mthd 1591 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c .mthd = gf100_grctx_pack_mthd, mthd 38 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.h const struct gf100_gr_pack *mthd; mthd 92 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf104.c .mthd = gf100_grctx_pack_mthd, mthd 793 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf108.c .mthd = gf108_grctx_pack_mthd, mthd 340 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf110.c .mthd = gf110_grctx_pack_mthd, mthd 292 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf117.c .mthd = gf119_grctx_pack_mthd, mthd 508 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf119.c .mthd = gf119_grctx_pack_mthd, mthd 987 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk104.c .mthd = gk104_grctx_pack_mthd, mthd 834 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk110.c .mthd = gk110_grctx_pack_mthd, mthd 83 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk110b.c .mthd = gk110_grctx_pack_mthd, mthd 549 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk208.c .mthd = gk110_grctx_pack_mthd, mthd 974 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm107.c .mthd = gm107_grctx_pack_mthd, mthd 231 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gf100_fermi_mthd(struct nvkm_object *object, u32 mthd, void *data, u32 size) mthd 233 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c nvif_ioctl(object, "fermi mthd %08x\n", mthd); mthd 234 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c switch (mthd) { mthd 247 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c .mthd = gf100_fermi_mthd, mthd 258 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gf100_gr_mthd_sw(struct nvkm_device *device, u16 class, u32 mthd, u32 data) mthd 263 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c switch (mthd) { mthd 725 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gf100_gr_fecs_ctrl_ctxsw(struct gf100_gr *gr, u32 mthd) mthd 732 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c nvkm_wr32(device, 0x409504, mthd); mthd 932 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c u32 mthd = nvkm_rd32(gr->base.engine.subdev.device, 0x409808); mthd 933 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c if (mthd & 0x00080000) mthd 1518 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c u32 mthd = (addr & 0x00003ffc); mthd 1523 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c subc, class, mthd, data); mthd 1556 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c u32 mthd = (addr & 0x00003ffc); mthd 1585 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c if (!gf100_gr_mthd_sw(device, class, mthd, data)) { mthd 1589 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c class, mthd, data); mthd 1598 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c chid, inst << 12, name, subc, class, mthd, data); mthd 1609 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c name, subc, class, mthd, data); mthd 758 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c nv03_gr_mthd_gdi(struct nvkm_device *device, u32 inst, u32 mthd, u32 data) mthd 761 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c switch (mthd) { mthd 774 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c nv04_gr_mthd_gdi(struct nvkm_device *device, u32 inst, u32 mthd, u32 data) mthd 777 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c switch (mthd) { mthd 791 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c nv01_gr_mthd_blit(struct nvkm_device *device, u32 inst, u32 mthd, u32 data) mthd 794 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c switch (mthd) { mthd 810 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c nv04_gr_mthd_blit(struct nvkm_device *device, u32 inst, u32 mthd, u32 data) mthd 813 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c switch (mthd) { mthd 829 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c nv04_gr_mthd_iifc(struct nvkm_device *device, u32 inst, u32 mthd, u32 data) mthd 832 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c switch (mthd) { mthd 848 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c nv01_gr_mthd_ifc(struct nvkm_device *device, u32 inst, u32 mthd, u32 data) mthd 851 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c switch (mthd) { mthd 866 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c nv04_gr_mthd_ifc(struct nvkm_device *device, u32 inst, u32 mthd, u32 data) mthd 869 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c switch (mthd) { mthd 885 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c nv03_gr_mthd_sifc(struct nvkm_device *device, u32 inst, u32 mthd, u32 data) mthd 888 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c switch (mthd) { mthd 902 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c nv04_gr_mthd_sifc(struct nvkm_device *device, u32 inst, u32 mthd, u32 data) mthd 905 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c switch (mthd) { mthd 920 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c nv03_gr_mthd_sifm(struct nvkm_device *device, u32 inst, u32 mthd, u32 data) mthd 923 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c switch (mthd) { mthd 936 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c nv04_gr_mthd_sifm(struct nvkm_device *device, u32 inst, u32 mthd, u32 data) mthd 939 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c switch (mthd) { mthd 953 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c nv04_gr_mthd_surf3d(struct nvkm_device *device, u32 inst, u32 mthd, u32 data) mthd 956 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c switch (mthd) { mthd 966 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c nv03_gr_mthd_ttri(struct nvkm_device *device, u32 inst, u32 mthd, u32 data) mthd 969 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c switch (mthd) { mthd 980 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c nv01_gr_mthd_prim(struct nvkm_device *device, u32 inst, u32 mthd, u32 data) mthd 983 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c switch (mthd) { mthd 997 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c nv04_gr_mthd_prim(struct nvkm_device *device, u32 inst, u32 mthd, u32 data) mthd 1000 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c switch (mthd) { mthd 1015 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c nv04_gr_mthd(struct nvkm_device *device, u32 inst, u32 mthd, u32 data) mthd 1039 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c return func(device, inst, mthd, data); mthd 1283 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c u32 mthd = (addr & 0x00001ffc); mthd 1297 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c if (!nv04_gr_mthd(device, inst, mthd, data)) mthd 1321 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c subc, class, mthd, data); mthd 431 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c nv17_gr_mthd_lma_window(struct nv10_gr_chan *chan, u32 mthd, u32 data) mthd 440 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c chan->lma_window[(mthd - 0x1638) / 4] = data; mthd 442 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c if (mthd != 0x1644) mthd 504 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c nv17_gr_mthd_lma_enable(struct nv10_gr_chan *chan, u32 mthd, u32 data) mthd 516 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c nv17_gr_mthd_celcius(struct nv10_gr_chan *chan, u32 mthd, u32 data) mthd 519 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c switch (mthd) { mthd 526 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c func(chan, mthd, data); mthd 531 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c nv10_gr_mthd(struct nv10_gr_chan *chan, u8 class, u32 mthd, u32 data) mthd 539 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c return func(chan, mthd, data); mthd 1092 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c u32 mthd = (addr & 0x00001ffc); mthd 1105 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c if (!nv10_gr_mthd(chan, class, mthd, data)) mthd 1129 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c subc, class, mthd, data); mthd 192 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c u32 mthd = (addr & 0x00001ffc); mthd 213 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c subc, class, mthd, data); mthd 244 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c u32 mthd = (addr & 0x00001ffc); mthd 280 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c subc, class, mthd, data); mthd 424 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c u32 mthd = (addr & 0x00001ffc); mthd 436 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c chid, inst, name, subc, class, mthd, mthd 452 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c u32 mthd = (addr & 0x00001ffc); mthd 462 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c subc, class, mthd, data, addr); mthd 630 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c u32 mthd = (addr & 0x00001ffc); mthd 669 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c subc, class, mthd, data); mthd 125 drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.c nv31_mpeg_mthd_dma(struct nvkm_device *device, u32 mthd, u32 data) mthd 143 drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.c if (mthd == 0x0190) { mthd 150 drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.c if (mthd == 0x01a0) { mthd 169 drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.c nv31_mpeg_mthd(struct nv31_mpeg *mpeg, u32 mthd, u32 data) mthd 172 drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.c switch (mthd) { mthd 176 drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.c return mpeg->func->mthd_dma(device, mthd, data); mthd 191 drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.c u32 mthd = nvkm_rd32(device, 0x00b234); mthd 200 drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.c if (type == 0x00000020 && mthd == 0x0000) { mthd 206 drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.c if (nv31_mpeg_mthd(mpeg, mthd, data)) mthd 218 drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.c "unknown", stat, type, mthd, data); mthd 18 drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.h bool (*mthd_dma)(struct nvkm_device *, u32 mthd, u32 data); mthd 31 drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv40.c nv40_mpeg_mthd_dma(struct nvkm_device *device, u32 mthd, u32 data) mthd 50 drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv40.c if (mthd == 0x0190) { mthd 56 drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv40.c if (mthd == 0x01a0) { mthd 129 drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv44.c nv44_mpeg_mthd(struct nvkm_device *device, u32 mthd, u32 data) mthd 131 drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv44.c switch (mthd) { mthd 135 drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv44.c return nv40_mpeg_mthd_dma(device, mthd, data); mthd 153 drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv44.c u32 mthd = nvkm_rd32(device, 0x00b234); mthd 169 drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv44.c if (type == 0x00000020 && mthd == 0x0000) { mthd 175 drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv44.c if (nv44_mpeg_mthd(subdev->device, mthd, data)) mthd 187 drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv44.c stat, type, mthd, data); mthd 67 drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv50.c u32 mthd = nvkm_rd32(device, 0x00b234); mthd 73 drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv50.c if (type == 0x00000020 && mthd == 0x0000) { mthd 81 drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv50.c stat, type, mthd, data); mthd 293 drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c nvkm_perfdom_mthd(struct nvkm_object *object, u32 mthd, void *data, u32 size) mthd 296 drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c switch (mthd) { mthd 362 drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c .mthd = nvkm_perfdom_mthd, mthd 588 drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c nvkm_perfmon_mthd(struct nvkm_object *object, u32 mthd, void *data, u32 size) mthd 591 drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c switch (mthd) { mthd 641 drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c .mthd = nvkm_perfmon_mthd, mthd 49 drivers/gpu/drm/nouveau/nvkm/engine/sec/g98.c u32 mthd = (addr & 0x07ff) << 2; mthd 60 drivers/gpu/drm/nouveau/nvkm/engine/sec/g98.c subc, mthd, data); mthd 30 drivers/gpu/drm/nouveau/nvkm/engine/sw/base.c nvkm_sw_mthd(struct nvkm_sw *sw, int chid, int subc, u32 mthd, u32 data) mthd 39 drivers/gpu/drm/nouveau/nvkm/engine/sw/base.c handled = nvkm_sw_chan_mthd(chan, subc, mthd, data); mthd 33 drivers/gpu/drm/nouveau/nvkm/engine/sw/chan.c nvkm_sw_chan_mthd(struct nvkm_sw_chan *chan, int subc, u32 mthd, u32 data) mthd 35 drivers/gpu/drm/nouveau/nvkm/engine/sw/chan.c switch (mthd) { mthd 42 drivers/gpu/drm/nouveau/nvkm/engine/sw/chan.c if (chan->func->mthd) mthd 43 drivers/gpu/drm/nouveau/nvkm/engine/sw/chan.c return chan->func->mthd(chan, subc, mthd, data); mthd 22 drivers/gpu/drm/nouveau/nvkm/engine/sw/chan.h bool (*mthd)(struct nvkm_sw_chan *, int subc, u32 mthd, u32 data); mthd 28 drivers/gpu/drm/nouveau/nvkm/engine/sw/chan.h bool nvkm_sw_chan_mthd(struct nvkm_sw_chan *, int subc, u32 mthd, u32 data); mthd 57 drivers/gpu/drm/nouveau/nvkm/engine/sw/gf100.c gf100_sw_chan_mthd(struct nvkm_sw_chan *base, int subc, u32 mthd, u32 data) mthd 62 drivers/gpu/drm/nouveau/nvkm/engine/sw/gf100.c switch (mthd) { mthd 101 drivers/gpu/drm/nouveau/nvkm/engine/sw/gf100.c .mthd = gf100_sw_chan_mthd, mthd 60 drivers/gpu/drm/nouveau/nvkm/engine/sw/nv04.c nv04_nvsw_mthd(struct nvkm_nvsw *nvsw, u32 mthd, void *data, u32 size) mthd 62 drivers/gpu/drm/nouveau/nvkm/engine/sw/nv04.c switch (mthd) { mthd 73 drivers/gpu/drm/nouveau/nvkm/engine/sw/nv04.c .mthd = nv04_nvsw_mthd, mthd 88 drivers/gpu/drm/nouveau/nvkm/engine/sw/nv04.c nv04_sw_chan_mthd(struct nvkm_sw_chan *base, int subc, u32 mthd, u32 data) mthd 92 drivers/gpu/drm/nouveau/nvkm/engine/sw/nv04.c switch (mthd) { mthd 105 drivers/gpu/drm/nouveau/nvkm/engine/sw/nv04.c .mthd = nv04_sw_chan_mthd, mthd 62 drivers/gpu/drm/nouveau/nvkm/engine/sw/nv50.c nv50_sw_chan_mthd(struct nvkm_sw_chan *base, int subc, u32 mthd, u32 data) mthd 67 drivers/gpu/drm/nouveau/nvkm/engine/sw/nv50.c switch (mthd) { mthd 96 drivers/gpu/drm/nouveau/nvkm/engine/sw/nv50.c .mthd = nv50_sw_chan_mthd, mthd 30 drivers/gpu/drm/nouveau/nvkm/engine/sw/nvsw.c nvkm_nvsw_mthd_(struct nvkm_object *object, u32 mthd, void *data, u32 size) mthd 33 drivers/gpu/drm/nouveau/nvkm/engine/sw/nvsw.c if (nvsw->func->mthd) mthd 34 drivers/gpu/drm/nouveau/nvkm/engine/sw/nvsw.c return nvsw->func->mthd(nvsw, mthd, data, size); mthd 39 drivers/gpu/drm/nouveau/nvkm/engine/sw/nvsw.c nvkm_nvsw_ntfy_(struct nvkm_object *object, u32 mthd, mthd 43 drivers/gpu/drm/nouveau/nvkm/engine/sw/nvsw.c switch (mthd) { mthd 55 drivers/gpu/drm/nouveau/nvkm/engine/sw/nvsw.c .mthd = nvkm_nvsw_mthd_, mthd 14 drivers/gpu/drm/nouveau/nvkm/engine/sw/nvsw.h int (*mthd)(struct nvkm_nvsw *, u32 mthd, void *data, u32 size); mthd 39 drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadow.c shadow_fetch(struct nvkm_bios *bios, struct shadow *mthd, u32 upto) mthd 43 drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadow.c void *data = mthd->data; mthd 45 drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadow.c u32 read = mthd->func->read(data, start, limit - start, bios); mthd 52 drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadow.c shadow_image(struct nvkm_bios *bios, int idx, u32 offset, struct shadow *mthd) mthd 58 drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadow.c if (mthd->func->no_pcir) { mthd 61 drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadow.c image.size = mthd->func->size(mthd->data); mthd 64 drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadow.c if (!shadow_fetch(bios, mthd, offset + 0x1000)) { mthd 78 drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadow.c if (!shadow_fetch(bios, mthd, image.size)) { mthd 85 drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadow.c if (!mthd->func->ignore_checksum && mthd 89 drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadow.c if (!mthd->func->require_checksum) { mthd 90 drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadow.c if (mthd->func->rw) mthd 105 drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadow.c score += shadow_image(bios, idx + 1, offset + image.size, mthd); mthd 110 drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadow.c shadow_method(struct nvkm_bios *bios, struct shadow *mthd, const char *name) mthd 112 drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadow.c const struct nvbios_source *func = mthd->func; mthd 117 drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadow.c mthd->data = func->init(bios, name); mthd 118 drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadow.c if (IS_ERR(mthd->data)) { mthd 119 drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadow.c mthd->data = NULL; mthd 123 drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadow.c mthd->score = shadow_image(bios, 0, 0, mthd); mthd 125 drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadow.c func->fini(mthd->data); mthd 126 drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadow.c nvkm_debug(subdev, "scored %d\n", mthd->score); mthd 127 drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadow.c mthd->data = bios->data; mthd 128 drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadow.c mthd->size = bios->size; mthd 132 drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadow.c return mthd->score; mthd 180 drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadow.c }, *mthd, *best = NULL; mthd 190 drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadow.c for (mthd = mthds; mthd->func; mthd++) { mthd 191 drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadow.c if (mthd->func->name && mthd 192 drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadow.c !strcasecmp(source, mthd->func->name)) { mthd 193 drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadow.c best = mthd; mthd 194 drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadow.c if (shadow_method(bios, mthd, NULL)) mthd 200 drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadow.c if (!best && (best = mthd)) { mthd 201 drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadow.c mthd->func = &shadow_fw; mthd 202 drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadow.c shadow_method(bios, mthd, source); mthd 203 drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadow.c mthd->func = NULL; mthd 215 drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadow.c for (mthd = mthds, best = mthd; mthd->func; mthd++) { mthd 216 drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadow.c if (!mthd->skip || best->score < mthd->skip) { mthd 217 drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadow.c if (shadow_method(bios, mthd, NULL)) { mthd 218 drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadow.c if (mthd->score > best->score) mthd 219 drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadow.c best = mthd; mthd 226 drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadow.c for (mthd = mthds; mthd->func; mthd++) { mthd 227 drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadow.c if (mthd != best) mthd 228 drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadow.c kfree(mthd->data); mthd 131 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/ummu.c nvkm_ummu_mthd(struct nvkm_object *object, u32 mthd, void *argv, u32 argc) mthd 134 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/ummu.c switch (mthd) { mthd 146 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/ummu.c .mthd = nvkm_ummu_mthd, mthd 333 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/uvmm.c nvkm_uvmm_mthd(struct nvkm_object *object, u32 mthd, void *argv, u32 argc) mthd 336 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/uvmm.c switch (mthd) { mthd 345 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/uvmm.c if (uvmm->vmm->func->mthd) { mthd 346 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/uvmm.c return uvmm->vmm->func->mthd(uvmm->vmm, mthd 348 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/uvmm.c mthd, argv, argc); mthd 368 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/uvmm.c .mthd = nvkm_uvmm_mthd, mthd 148 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmm.h int (*mthd)(struct nvkm_vmm *, struct nvkm_client *, mthd 149 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmm.h u32 mthd, void *argv, u32 argc); mthd 442 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgp100.c struct nvkm_client *client, u32 mthd, void *argv, u32 argc) mthd 445 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgp100.c switch (mthd) { mthd 494 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgp100.c .mthd = gp100_vmm_mthd, mthd 31 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgp10b.c .mthd = gp100_vmm_mthd, mthd 69 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgv100.c .mthd = gp100_vmm_mthd, mthd 59 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmtu102.c .mthd = gp100_vmm_mthd, mthd 11 drivers/gpu/drm/nouveau/nvkm/subdev/pmu/memx.c u32 mthd; mthd 23 drivers/gpu/drm/nouveau/nvkm/subdev/pmu/memx.c if (memx->c.mthd) { mthd 24 drivers/gpu/drm/nouveau/nvkm/subdev/pmu/memx.c nvkm_wr32(device, 0x10a1c4, (memx->c.size << 16) | memx->c.mthd); mthd 27 drivers/gpu/drm/nouveau/nvkm/subdev/pmu/memx.c memx->c.mthd = 0; mthd 33 drivers/gpu/drm/nouveau/nvkm/subdev/pmu/memx.c memx_cmd(struct nvkm_memx *memx, u32 mthd, u32 size, u32 data[]) mthd 36 drivers/gpu/drm/nouveau/nvkm/subdev/pmu/memx.c (memx->c.mthd && memx->c.mthd != mthd)) mthd 40 drivers/gpu/drm/nouveau/nvkm/subdev/pmu/memx.c memx->c.mthd = mthd;