mstm 671 drivers/gpu/drm/nouveau/dispnv50/disp.c struct nv50_mstm *mstm; mstm 692 drivers/gpu/drm/nouveau/dispnv50/disp.c struct nv50_mstm *mstm = mstc->mstm; mstm 695 drivers/gpu/drm/nouveau/dispnv50/disp.c WARN_ON(!mutex_is_locked(&mstm->mgr.payload_lock)); mstm 698 drivers/gpu/drm/nouveau/dispnv50/disp.c for (i = 0; i < mstm->mgr.max_payloads; i++) { mstm 699 drivers/gpu/drm/nouveau/dispnv50/disp.c struct drm_dp_payload *payload = &mstm->mgr.payloads[i]; mstm 701 drivers/gpu/drm/nouveau/dispnv50/disp.c mstm->outp->base.base.name, i, payload->vcpi, mstm 705 drivers/gpu/drm/nouveau/dispnv50/disp.c for (i = 0; i < mstm->mgr.max_payloads; i++) { mstm 706 drivers/gpu/drm/nouveau/dispnv50/disp.c struct drm_dp_payload *payload = &mstm->mgr.payloads[i]; mstm 719 drivers/gpu/drm/nouveau/dispnv50/disp.c struct nv50_mstm *mstm = mstc->mstm; mstm 726 drivers/gpu/drm/nouveau/dispnv50/disp.c drm_dp_mst_deallocate_vcpi(&mstm->mgr, mstc->port); mstm 738 drivers/gpu/drm/nouveau/dispnv50/disp.c struct nv50_mstm *mstm = mstc->mstm; mstm 745 drivers/gpu/drm/nouveau/dispnv50/disp.c .base.hasht = mstm->outp->dcb->hasht, mstm 746 drivers/gpu/drm/nouveau/dispnv50/disp.c .base.hashm = (0xf0ff & mstm->outp->dcb->hashm) | mstm 750 drivers/gpu/drm/nouveau/dispnv50/disp.c mutex_lock(&mstm->mgr.payload_lock); mstm 769 drivers/gpu/drm/nouveau/dispnv50/disp.c mutex_unlock(&mstm->mgr.payload_lock); mstm 780 drivers/gpu/drm/nouveau/dispnv50/disp.c struct nv50_mstm *mstm = mstc->mstm; mstm 812 drivers/gpu/drm/nouveau/dispnv50/disp.c slots = drm_dp_atomic_find_vcpi_slots(state, &mstm->mgr, mstc->port, mstm 840 drivers/gpu/drm/nouveau/dispnv50/disp.c struct nv50_mstm *mstm = NULL; mstm 850 drivers/gpu/drm/nouveau/dispnv50/disp.c mstm = mstc->mstm; mstm 859 drivers/gpu/drm/nouveau/dispnv50/disp.c r = drm_dp_mst_allocate_vcpi(&mstm->mgr, mstc->port, armh->dp.pbn, mstm 864 drivers/gpu/drm/nouveau/dispnv50/disp.c if (!mstm->links++) mstm 865 drivers/gpu/drm/nouveau/dispnv50/disp.c nv50_outp_acquire(mstm->outp); mstm 867 drivers/gpu/drm/nouveau/dispnv50/disp.c if (mstm->outp->link & 1) mstm 872 drivers/gpu/drm/nouveau/dispnv50/disp.c mstm->outp->update(mstm->outp, head->base.index, armh, proto, mstm 877 drivers/gpu/drm/nouveau/dispnv50/disp.c mstm->modified = true; mstm 885 drivers/gpu/drm/nouveau/dispnv50/disp.c struct nv50_mstm *mstm = mstc->mstm; mstm 887 drivers/gpu/drm/nouveau/dispnv50/disp.c drm_dp_mst_reset_vcpi_slots(&mstm->mgr, mstc->port); mstm 889 drivers/gpu/drm/nouveau/dispnv50/disp.c mstm->outp->update(mstm->outp, msto->head->base.index, NULL, 0, 0); mstm 890 drivers/gpu/drm/nouveau/dispnv50/disp.c mstm->modified = true; mstm 891 drivers/gpu/drm/nouveau/dispnv50/disp.c if (!--mstm->links) mstm 892 drivers/gpu/drm/nouveau/dispnv50/disp.c mstm->disabled = true; mstm 946 drivers/gpu/drm/nouveau/dispnv50/disp.c return &mstc->mstm->msto[head->base.index]->encoder; mstm 954 drivers/gpu/drm/nouveau/dispnv50/disp.c return &mstc->mstm->msto[0]->encoder; mstm 989 drivers/gpu/drm/nouveau/dispnv50/disp.c struct drm_dp_mst_topology_mgr *mgr = &mstc->mstm->mgr; mstm 1070 drivers/gpu/drm/nouveau/dispnv50/disp.c nv50_mstc_new(struct nv50_mstm *mstm, struct drm_dp_mst_port *port, mstm 1073 drivers/gpu/drm/nouveau/dispnv50/disp.c struct drm_device *dev = mstm->outp->base.base.dev; mstm 1079 drivers/gpu/drm/nouveau/dispnv50/disp.c mstc->mstm = mstm; mstm 1095 drivers/gpu/drm/nouveau/dispnv50/disp.c for (i = 0; i < ARRAY_SIZE(mstm->msto) && mstm->msto[i]; i++) mstm 1096 drivers/gpu/drm/nouveau/dispnv50/disp.c drm_connector_attach_encoder(&mstc->connector, &mstm->msto[i]->encoder); mstm 1106 drivers/gpu/drm/nouveau/dispnv50/disp.c nv50_mstm_cleanup(struct nv50_mstm *mstm) mstm 1108 drivers/gpu/drm/nouveau/dispnv50/disp.c struct nouveau_drm *drm = nouveau_drm(mstm->outp->base.base.dev); mstm 1112 drivers/gpu/drm/nouveau/dispnv50/disp.c NV_ATOMIC(drm, "%s: mstm cleanup\n", mstm->outp->base.base.name); mstm 1113 drivers/gpu/drm/nouveau/dispnv50/disp.c ret = drm_dp_check_act_status(&mstm->mgr); mstm 1115 drivers/gpu/drm/nouveau/dispnv50/disp.c ret = drm_dp_update_payload_part2(&mstm->mgr); mstm 1117 drivers/gpu/drm/nouveau/dispnv50/disp.c drm_for_each_encoder(encoder, mstm->outp->base.base.dev) { mstm 1121 drivers/gpu/drm/nouveau/dispnv50/disp.c if (mstc && mstc->mstm == mstm) mstm 1126 drivers/gpu/drm/nouveau/dispnv50/disp.c mstm->modified = false; mstm 1130 drivers/gpu/drm/nouveau/dispnv50/disp.c nv50_mstm_prepare(struct nv50_mstm *mstm) mstm 1132 drivers/gpu/drm/nouveau/dispnv50/disp.c struct nouveau_drm *drm = nouveau_drm(mstm->outp->base.base.dev); mstm 1136 drivers/gpu/drm/nouveau/dispnv50/disp.c NV_ATOMIC(drm, "%s: mstm prepare\n", mstm->outp->base.base.name); mstm 1137 drivers/gpu/drm/nouveau/dispnv50/disp.c ret = drm_dp_update_payload_part1(&mstm->mgr); mstm 1139 drivers/gpu/drm/nouveau/dispnv50/disp.c drm_for_each_encoder(encoder, mstm->outp->base.base.dev) { mstm 1143 drivers/gpu/drm/nouveau/dispnv50/disp.c if (mstc && mstc->mstm == mstm) mstm 1148 drivers/gpu/drm/nouveau/dispnv50/disp.c if (mstm->disabled) { mstm 1149 drivers/gpu/drm/nouveau/dispnv50/disp.c if (!mstm->links) mstm 1150 drivers/gpu/drm/nouveau/dispnv50/disp.c nv50_outp_release(mstm->outp); mstm 1151 drivers/gpu/drm/nouveau/dispnv50/disp.c mstm->disabled = false; mstm 1183 drivers/gpu/drm/nouveau/dispnv50/disp.c struct nv50_mstm *mstm = nv50_mstm(mgr); mstm 1187 drivers/gpu/drm/nouveau/dispnv50/disp.c ret = nv50_mstc_new(mstm, port, path, &mstc); mstm 1202 drivers/gpu/drm/nouveau/dispnv50/disp.c nv50_mstm_service(struct nv50_mstm *mstm) mstm 1204 drivers/gpu/drm/nouveau/dispnv50/disp.c struct drm_dp_aux *aux = mstm ? mstm->mgr.aux : NULL; mstm 1215 drivers/gpu/drm/nouveau/dispnv50/disp.c drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, false); mstm 1219 drivers/gpu/drm/nouveau/dispnv50/disp.c drm_dp_mst_hpd_irq(&mstm->mgr, esi, &handled); mstm 1228 drivers/gpu/drm/nouveau/dispnv50/disp.c nv50_mstm_remove(struct nv50_mstm *mstm) mstm 1230 drivers/gpu/drm/nouveau/dispnv50/disp.c if (mstm) mstm 1231 drivers/gpu/drm/nouveau/dispnv50/disp.c drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, false); mstm 1235 drivers/gpu/drm/nouveau/dispnv50/disp.c nv50_mstm_enable(struct nv50_mstm *mstm, u8 dpcd, int state) mstm 1237 drivers/gpu/drm/nouveau/dispnv50/disp.c struct nouveau_encoder *outp = mstm->outp; mstm 1257 drivers/gpu/drm/nouveau/dispnv50/disp.c ret = drm_dp_dpcd_writeb(mstm->mgr.aux, DP_MSTM_CTRL, 0); mstm 1263 drivers/gpu/drm/nouveau/dispnv50/disp.c ret = drm_dp_dpcd_writeb(mstm->mgr.aux, DP_MSTM_CTRL, mstm 1274 drivers/gpu/drm/nouveau/dispnv50/disp.c nv50_mstm_detect(struct nv50_mstm *mstm, u8 dpcd[8], int allow) mstm 1281 drivers/gpu/drm/nouveau/dispnv50/disp.c if (!mstm) mstm 1284 drivers/gpu/drm/nouveau/dispnv50/disp.c mutex_lock(&mstm->mgr.lock); mstm 1286 drivers/gpu/drm/nouveau/dispnv50/disp.c old_state = mstm->mgr.mst_state; mstm 1288 drivers/gpu/drm/nouveau/dispnv50/disp.c aux = mstm->mgr.aux; mstm 1309 drivers/gpu/drm/nouveau/dispnv50/disp.c mutex_unlock(&mstm->mgr.lock); mstm 1313 drivers/gpu/drm/nouveau/dispnv50/disp.c ret = nv50_mstm_enable(mstm, dpcd[0], new_state); mstm 1317 drivers/gpu/drm/nouveau/dispnv50/disp.c mutex_unlock(&mstm->mgr.lock); mstm 1319 drivers/gpu/drm/nouveau/dispnv50/disp.c ret = drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, new_state); mstm 1321 drivers/gpu/drm/nouveau/dispnv50/disp.c return nv50_mstm_enable(mstm, dpcd[0], 0); mstm 1326 drivers/gpu/drm/nouveau/dispnv50/disp.c mutex_unlock(&mstm->mgr.lock); mstm 1331 drivers/gpu/drm/nouveau/dispnv50/disp.c nv50_mstm_fini(struct nv50_mstm *mstm) mstm 1333 drivers/gpu/drm/nouveau/dispnv50/disp.c if (mstm && mstm->mgr.mst_state) mstm 1334 drivers/gpu/drm/nouveau/dispnv50/disp.c drm_dp_mst_topology_mgr_suspend(&mstm->mgr); mstm 1338 drivers/gpu/drm/nouveau/dispnv50/disp.c nv50_mstm_init(struct nv50_mstm *mstm) mstm 1342 drivers/gpu/drm/nouveau/dispnv50/disp.c if (!mstm || !mstm->mgr.mst_state) mstm 1345 drivers/gpu/drm/nouveau/dispnv50/disp.c ret = drm_dp_mst_topology_mgr_resume(&mstm->mgr); mstm 1347 drivers/gpu/drm/nouveau/dispnv50/disp.c drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, false); mstm 1348 drivers/gpu/drm/nouveau/dispnv50/disp.c drm_kms_helper_hotplug_event(mstm->mgr.dev); mstm 1355 drivers/gpu/drm/nouveau/dispnv50/disp.c struct nv50_mstm *mstm = *pmstm; mstm 1356 drivers/gpu/drm/nouveau/dispnv50/disp.c if (mstm) { mstm 1357 drivers/gpu/drm/nouveau/dispnv50/disp.c drm_dp_mst_topology_mgr_destroy(&mstm->mgr); mstm 1369 drivers/gpu/drm/nouveau/dispnv50/disp.c struct nv50_mstm *mstm; mstm 1383 drivers/gpu/drm/nouveau/dispnv50/disp.c if (!(mstm = *pmstm = kzalloc(sizeof(*mstm), GFP_KERNEL))) mstm 1385 drivers/gpu/drm/nouveau/dispnv50/disp.c mstm->outp = outp; mstm 1386 drivers/gpu/drm/nouveau/dispnv50/disp.c mstm->mgr.cbs = &nv50_mstm; mstm 1388 drivers/gpu/drm/nouveau/dispnv50/disp.c ret = drm_dp_mst_topology_mgr_init(&mstm->mgr, dev, aux, aux_max, mstm 1395 drivers/gpu/drm/nouveau/dispnv50/disp.c i, &mstm->msto[i]); mstm 1562 drivers/gpu/drm/nouveau/dispnv50/disp.c nv50_mstm_del(&nv_encoder->dp.mstm); mstm 1631 drivers/gpu/drm/nouveau/dispnv50/disp.c &nv_encoder->dp.mstm); mstm 1780 drivers/gpu/drm/nouveau/dispnv50/disp.c struct nv50_mstm *mstm; mstm 1787 drivers/gpu/drm/nouveau/dispnv50/disp.c mstm = nouveau_encoder(encoder)->dp.mstm; mstm 1788 drivers/gpu/drm/nouveau/dispnv50/disp.c if (mstm && mstm->modified) mstm 1789 drivers/gpu/drm/nouveau/dispnv50/disp.c nv50_mstm_prepare(mstm); mstm 1801 drivers/gpu/drm/nouveau/dispnv50/disp.c mstm = nouveau_encoder(encoder)->dp.mstm; mstm 1802 drivers/gpu/drm/nouveau/dispnv50/disp.c if (mstm && mstm->modified) mstm 1803 drivers/gpu/drm/nouveau/dispnv50/disp.c nv50_mstm_cleanup(mstm); mstm 2268 drivers/gpu/drm/nouveau/dispnv50/disp.c nv50_mstm_fini(nv_encoder->dp.mstm); mstm 2286 drivers/gpu/drm/nouveau/dispnv50/disp.c nv50_mstm_init(nv_encoder->dp.mstm); mstm 1154 drivers/gpu/drm/nouveau/nouveau_connector.c nv50_mstm_service(nv_encoder->dp.mstm); mstm 1183 drivers/gpu/drm/nouveau/nouveau_connector.c nv50_mstm_remove(nv_encoder->dp.mstm); mstm 94 drivers/gpu/drm/nouveau/nouveau_dp.c ret = nv50_mstm_detect(nv_encoder->dp.mstm, dpcd, nouveau_mst); mstm 63 drivers/gpu/drm/nouveau/nouveau_encoder.h struct nv50_mstm *mstm;