msr_offset 61 arch/x86/events/intel/uncore.h unsigned msr_offset; msr_offset 240 arch/x86/events/intel/uncore.h pmu->type->msr_offset * pmu->pmu_idx; msr_offset 433 arch/x86/events/intel/uncore_nhmex.c .msr_offset = NHMEX_B_MSR_OFFSET, msr_offset 510 arch/x86/events/intel/uncore_nhmex.c .msr_offset = NHMEX_S_MSR_OFFSET, msr_offset 784 arch/x86/events/intel/uncore_nhmex.c msr = er->msr + type->msr_offset * box->pmu->pmu_idx; msr_offset 936 arch/x86/events/intel/uncore_nhmex.c .msr_offset = NHMEX_M_MSR_OFFSET, msr_offset 1199 arch/x86/events/intel/uncore_nhmex.c .msr_offset = NHMEX_R_MSR_OFFSET, msr_offset 202 arch/x86/events/intel/uncore_snb.c .msr_offset = SNB_UNC_CBO_MSR_OFFSET, msr_offset 216 arch/x86/events/intel/uncore_snb.c .msr_offset = SNB_UNC_ARB_MSR_OFFSET, msr_offset 280 arch/x86/events/intel/uncore_snb.c .msr_offset = SNB_UNC_CBO_MSR_OFFSET, msr_offset 307 arch/x86/events/intel/uncore_snb.c .msr_offset = ICL_UNC_CBO_MSR_OFFSET, msr_offset 963 arch/x86/events/intel/uncore_snbep.c .msr_offset = SNBEP_CBO_MSR_OFFSET, msr_offset 1666 arch/x86/events/intel/uncore_snbep.c .msr_offset = SNBEP_CBO_MSR_OFFSET, msr_offset 2087 arch/x86/events/intel/uncore_snbep.c .msr_offset = KNL_CHA_MSR_OFFSET, msr_offset 2650 arch/x86/events/intel/uncore_snbep.c .msr_offset = HSWEP_CBO_MSR_OFFSET, msr_offset 2705 arch/x86/events/intel/uncore_snbep.c .msr_offset = HSWEP_SBOX_MSR_OFFSET, msr_offset 3090 arch/x86/events/intel/uncore_snbep.c .msr_offset = HSWEP_CBO_MSR_OFFSET, msr_offset 3106 arch/x86/events/intel/uncore_snbep.c .msr_offset = HSWEP_SBOX_MSR_OFFSET, msr_offset 3528 arch/x86/events/intel/uncore_snbep.c .msr_offset = HSWEP_CBO_MSR_OFFSET, msr_offset 3588 arch/x86/events/intel/uncore_snbep.c .msr_offset = SKX_IIO_MSR_OFFSET, msr_offset 3699 arch/x86/events/intel/uncore_snbep.c .msr_offset = SKX_IRP_MSR_OFFSET, msr_offset 4072 arch/x86/events/intel/uncore_snbep.c box->pmu->type->msr_offset * box->pmu->pmu_idx; msr_offset 4109 arch/x86/events/intel/uncore_snbep.c .msr_offset = HSWEP_CBO_MSR_OFFSET, msr_offset 4142 arch/x86/events/intel/uncore_snbep.c .msr_offset = SNR_IIO_MSR_OFFSET, msr_offset 4156 arch/x86/events/intel/uncore_snbep.c .msr_offset = SNR_IRP_MSR_OFFSET, msr_offset 4169 arch/x86/events/intel/uncore_snbep.c .msr_offset = SNR_M2PCIE_MSR_OFFSET, msr_offset 679 tools/power/x86/x86_energy_perf_policy/x86_energy_perf_policy.c void read_hwp_cap(int cpu, struct msr_hwp_cap *cap, unsigned int msr_offset) msr_offset 683 tools/power/x86/x86_energy_perf_policy/x86_energy_perf_policy.c get_msr(cpu, msr_offset, &msr); msr_offset 714 tools/power/x86/x86_energy_perf_policy/x86_energy_perf_policy.c void read_hwp_request(int cpu, struct msr_hwp_request *hwp_req, unsigned int msr_offset) msr_offset 718 tools/power/x86/x86_energy_perf_policy/x86_energy_perf_policy.c get_msr(cpu, msr_offset, &msr); msr_offset 728 tools/power/x86/x86_energy_perf_policy/x86_energy_perf_policy.c void write_hwp_request(int cpu, struct msr_hwp_request *hwp_req, unsigned int msr_offset) msr_offset 745 tools/power/x86/x86_energy_perf_policy/x86_energy_perf_policy.c put_msr(cpu, msr_offset, msr); msr_offset 940 tools/power/x86/x86_energy_perf_policy/x86_energy_perf_policy.c int msr_offset = MSR_HWP_REQUEST; msr_offset 942 tools/power/x86/x86_energy_perf_policy/x86_energy_perf_policy.c read_hwp_request(cpu, &req, msr_offset); msr_offset 972 tools/power/x86/x86_energy_perf_policy/x86_energy_perf_policy.c write_hwp_request(cpu, &req, msr_offset); msr_offset 975 tools/power/x86/x86_energy_perf_policy/x86_energy_perf_policy.c read_hwp_request(cpu, &req, msr_offset); msr_offset 986 tools/power/x86/x86_energy_perf_policy/x86_energy_perf_policy.c int msr_offset = MSR_HWP_REQUEST_PKG; msr_offset 988 tools/power/x86/x86_energy_perf_policy/x86_energy_perf_policy.c read_hwp_request(cpu, &req, msr_offset); msr_offset 1016 tools/power/x86/x86_energy_perf_policy/x86_energy_perf_policy.c write_hwp_request(cpu, &req, msr_offset); msr_offset 1019 tools/power/x86/x86_energy_perf_policy/x86_energy_perf_policy.c read_hwp_request(cpu, &req, msr_offset);