msr_base           46 arch/x86/events/amd/uncore.c 	u32 msr_base;
msr_base          156 arch/x86/events/amd/uncore.c 	hwc->config_base = uncore->msr_base + (2 * hwc->idx);
msr_base          157 arch/x86/events/amd/uncore.c 	hwc->event_base = uncore->msr_base + 1 + (2 * hwc->idx);
msr_base          337 arch/x86/events/amd/uncore.c 		uncore_nb->msr_base = MSR_F15H_NB_PERF_CTL;
msr_base          351 arch/x86/events/amd/uncore.c 		uncore_llc->msr_base = MSR_F16H_L2I_PERF_CTL;
msr_base           68 arch/x86/kernel/cpu/resctrl/core.c 		.msr_base		= MSR_IA32_L3_CBM_BASE,
msr_base           85 arch/x86/kernel/cpu/resctrl/core.c 		.msr_base		= MSR_IA32_L3_CBM_BASE,
msr_base          102 arch/x86/kernel/cpu/resctrl/core.c 		.msr_base		= MSR_IA32_L3_CBM_BASE,
msr_base          119 arch/x86/kernel/cpu/resctrl/core.c 		.msr_base		= MSR_IA32_L2_CBM_BASE,
msr_base          136 arch/x86/kernel/cpu/resctrl/core.c 		.msr_base		= MSR_IA32_L2_CBM_BASE,
msr_base          153 arch/x86/kernel/cpu/resctrl/core.c 		.msr_base		= MSR_IA32_L2_CBM_BASE,
msr_base          368 arch/x86/kernel/cpu/resctrl/core.c 		wrmsrl(r->msr_base + i, d->ctrl_val[i]);
msr_base          393 arch/x86/kernel/cpu/resctrl/core.c 		wrmsrl(r->msr_base + i, delay_bw_map(d->ctrl_val[i], r));
msr_base          402 arch/x86/kernel/cpu/resctrl/core.c 		wrmsrl(r->msr_base + cbm_idx(r, i), d->ctrl_val[i]);
msr_base          924 arch/x86/kernel/cpu/resctrl/core.c 			r->msr_base = MSR_IA32_MBA_THRTL_BASE;
msr_base          944 arch/x86/kernel/cpu/resctrl/core.c 			r->msr_base = MSR_IA32_MBA_BW_BASE;
msr_base          448 arch/x86/kernel/cpu/resctrl/internal.h 	unsigned int		msr_base;
msr_base          415 arch/x86/kernel/cpu/resctrl/monitor.c 	cur_msr = r_mba->msr_base + closid;