msic 78 arch/powerpc/platforms/cell/axon_msi.c void axon_msi_debug_setup(struct device_node *dn, struct axon_msic *msic); msic 81 arch/powerpc/platforms/cell/axon_msi.c struct axon_msic *msic) { } msic 85 arch/powerpc/platforms/cell/axon_msi.c static void msic_dcr_write(struct axon_msic *msic, unsigned int dcr_n, u32 val) msic 89 arch/powerpc/platforms/cell/axon_msi.c dcr_write(msic->dcr_host, dcr_n, val); msic 95 arch/powerpc/platforms/cell/axon_msi.c struct axon_msic *msic = irq_desc_get_handler_data(desc); msic 100 arch/powerpc/platforms/cell/axon_msi.c write_offset = dcr_read(msic->dcr_host, MSIC_WRITE_OFFSET_REG); msic 106 arch/powerpc/platforms/cell/axon_msi.c while (msic->read_offset != write_offset && retry < 100) { msic 107 arch/powerpc/platforms/cell/axon_msi.c idx = msic->read_offset / sizeof(__le32); msic 108 arch/powerpc/platforms/cell/axon_msi.c msi = le32_to_cpu(msic->fifo_virt[idx]); msic 112 arch/powerpc/platforms/cell/axon_msi.c write_offset, msic->read_offset, msi); msic 114 arch/powerpc/platforms/cell/axon_msi.c if (msi < nr_irqs && irq_get_chip_data(msi) == msic) { msic 116 arch/powerpc/platforms/cell/axon_msi.c msic->fifo_virt[idx] = cpu_to_le32(0xffffffff); msic 136 arch/powerpc/platforms/cell/axon_msi.c msic->read_offset += MSIC_FIFO_ENTRY_SIZE; msic 137 arch/powerpc/platforms/cell/axon_msi.c msic->read_offset &= MSIC_FIFO_SIZE_MASK; msic 143 arch/powerpc/platforms/cell/axon_msi.c msic->read_offset += MSIC_FIFO_ENTRY_SIZE; msic 144 arch/powerpc/platforms/cell/axon_msi.c msic->read_offset &= MSIC_FIFO_SIZE_MASK; msic 155 arch/powerpc/platforms/cell/axon_msi.c struct axon_msic *msic = NULL; msic 191 arch/powerpc/platforms/cell/axon_msi.c msic = irq_domain->host_data; msic 196 arch/powerpc/platforms/cell/axon_msi.c return msic; msic 258 arch/powerpc/platforms/cell/axon_msi.c struct axon_msic *msic; msic 260 arch/powerpc/platforms/cell/axon_msi.c msic = find_msi_translator(dev); msic 261 arch/powerpc/platforms/cell/axon_msi.c if (!msic) msic 269 arch/powerpc/platforms/cell/axon_msi.c virq = irq_create_direct_mapping(msic->irq_domain); msic 322 arch/powerpc/platforms/cell/axon_msi.c struct axon_msic *msic = dev_get_drvdata(&device->dev); msic 326 arch/powerpc/platforms/cell/axon_msi.c irq_domain_get_of_node(msic->irq_domain)); msic 327 arch/powerpc/platforms/cell/axon_msi.c tmp = dcr_read(msic->dcr_host, MSIC_CTRL_REG); msic 329 arch/powerpc/platforms/cell/axon_msi.c msic_dcr_write(msic, MSIC_CTRL_REG, tmp); msic 335 arch/powerpc/platforms/cell/axon_msi.c struct axon_msic *msic; msic 341 arch/powerpc/platforms/cell/axon_msi.c msic = kzalloc(sizeof(*msic), GFP_KERNEL); msic 342 arch/powerpc/platforms/cell/axon_msi.c if (!msic) { msic 358 arch/powerpc/platforms/cell/axon_msi.c msic->dcr_host = dcr_map(dn, dcr_base, dcr_len); msic 359 arch/powerpc/platforms/cell/axon_msi.c if (!DCR_MAP_OK(msic->dcr_host)) { msic 365 arch/powerpc/platforms/cell/axon_msi.c msic->fifo_virt = dma_alloc_coherent(&device->dev, MSIC_FIFO_SIZE_BYTES, msic 366 arch/powerpc/platforms/cell/axon_msi.c &msic->fifo_phys, GFP_KERNEL); msic 367 arch/powerpc/platforms/cell/axon_msi.c if (!msic->fifo_virt) { msic 379 arch/powerpc/platforms/cell/axon_msi.c memset(msic->fifo_virt, 0xff, MSIC_FIFO_SIZE_BYTES); msic 382 arch/powerpc/platforms/cell/axon_msi.c msic->irq_domain = irq_domain_add_nomap(dn, 65536, &msic_host_ops, msic); msic 383 arch/powerpc/platforms/cell/axon_msi.c if (!msic->irq_domain) { msic 389 arch/powerpc/platforms/cell/axon_msi.c irq_set_handler_data(virq, msic); msic 394 arch/powerpc/platforms/cell/axon_msi.c msic_dcr_write(msic, MSIC_BASE_ADDR_HI_REG, msic->fifo_phys >> 32); msic 395 arch/powerpc/platforms/cell/axon_msi.c msic_dcr_write(msic, MSIC_BASE_ADDR_LO_REG, msic 396 arch/powerpc/platforms/cell/axon_msi.c msic->fifo_phys & 0xFFFFFFFF); msic 397 arch/powerpc/platforms/cell/axon_msi.c msic_dcr_write(msic, MSIC_CTRL_REG, msic 401 arch/powerpc/platforms/cell/axon_msi.c msic->read_offset = dcr_read(msic->dcr_host, MSIC_WRITE_OFFSET_REG) msic 404 arch/powerpc/platforms/cell/axon_msi.c dev_set_drvdata(&device->dev, msic); msic 409 arch/powerpc/platforms/cell/axon_msi.c axon_msi_debug_setup(dn, msic); msic 416 arch/powerpc/platforms/cell/axon_msi.c dma_free_coherent(&device->dev, MSIC_FIFO_SIZE_BYTES, msic->fifo_virt, msic 417 arch/powerpc/platforms/cell/axon_msi.c msic->fifo_phys); msic 419 arch/powerpc/platforms/cell/axon_msi.c kfree(msic); msic 451 arch/powerpc/platforms/cell/axon_msi.c struct axon_msic *msic = data; msic 452 arch/powerpc/platforms/cell/axon_msi.c out_le32(msic->trigger, val); msic 464 arch/powerpc/platforms/cell/axon_msi.c void axon_msi_debug_setup(struct device_node *dn, struct axon_msic *msic) msic 475 arch/powerpc/platforms/cell/axon_msi.c msic->trigger = ioremap(addr, 0x4); msic 476 arch/powerpc/platforms/cell/axon_msi.c if (!msic->trigger) { msic 484 arch/powerpc/platforms/cell/axon_msi.c msic, &fops_msic)) { msic 40 arch/x86/include/asm/intel-mid.h u8 msic; msic 74 arch/x86/platform/intel-mid/device_libs/platform_mrfld_power_btn.c .msic = 1, msic 38 arch/x86/platform/intel-mid/device_libs/platform_msic_audio.c .msic = 1, msic 28 arch/x86/platform/intel-mid/device_libs/platform_msic_battery.c .msic = 1, msic 39 arch/x86/platform/intel-mid/device_libs/platform_msic_gpio.c .msic = 1, msic 40 arch/x86/platform/intel-mid/device_libs/platform_msic_ocd.c .msic = 1, msic 27 arch/x86/platform/intel-mid/device_libs/platform_msic_power_btn.c .msic = 1, msic 28 arch/x86/platform/intel-mid/device_libs/platform_msic_thermal.c .msic = 1, msic 345 arch/x86/platform/intel-mid/sfi.c if (dev->msic && intel_mid_has_msic()) msic 226 drivers/gpio/gpio-msic.c struct intel_msic *msic = pdev_to_intel_msic(mg->pdev); msic 233 drivers/gpio/gpio-msic.c intel_msic_irq_read(msic, INTEL_MSIC_GPIO0LVIRQ + i, &pin); msic 273 drivers/mfd/intel_msic.c int intel_msic_irq_read(struct intel_msic *msic, unsigned short reg, u8 *val) msic 278 drivers/mfd/intel_msic.c *val = readb(msic->irq_base + (reg - INTEL_MSIC_IRQLVL1)); msic 283 drivers/mfd/intel_msic.c static int intel_msic_init_devices(struct intel_msic *msic) msic 285 drivers/mfd/intel_msic.c struct platform_device *pdev = msic->pdev; msic 339 drivers/mfd/intel_msic.c static void intel_msic_remove_devices(struct intel_msic *msic) msic 341 drivers/mfd/intel_msic.c struct platform_device *pdev = msic->pdev; msic 349 drivers/mfd/intel_msic.c struct intel_msic *msic; msic 377 drivers/mfd/intel_msic.c msic = devm_kzalloc(&pdev->dev, sizeof(*msic), GFP_KERNEL); msic 378 drivers/mfd/intel_msic.c if (!msic) msic 381 drivers/mfd/intel_msic.c msic->vendor = MSIC_VENDOR(id0); msic 382 drivers/mfd/intel_msic.c msic->version = MSIC_VERSION(id0); msic 383 drivers/mfd/intel_msic.c msic->pdev = pdev; msic 390 drivers/mfd/intel_msic.c msic->irq_base = devm_ioremap_resource(&pdev->dev, res); msic 391 drivers/mfd/intel_msic.c if (IS_ERR(msic->irq_base)) msic 392 drivers/mfd/intel_msic.c return PTR_ERR(msic->irq_base); msic 394 drivers/mfd/intel_msic.c platform_set_drvdata(pdev, msic); msic 396 drivers/mfd/intel_msic.c ret = intel_msic_init_devices(msic); msic 403 drivers/mfd/intel_msic.c MSIC_MAJOR(msic->version), MSIC_MINOR(msic->version), msic 404 drivers/mfd/intel_msic.c msic->vendor); msic 411 drivers/mfd/intel_msic.c struct intel_msic *msic = platform_get_drvdata(pdev); msic 413 drivers/mfd/intel_msic.c intel_msic_remove_devices(msic); msic 450 include/linux/mfd/intel_msic.h extern int intel_msic_irq_read(struct intel_msic *msic, unsigned short reg,