msel              309 drivers/clk/nxp/clk-lpc18xx-cgu.c static u32 lpc18xx_pll0_msel2mdec(u32 msel)
msel              313 drivers/clk/nxp/clk-lpc18xx-cgu.c 	switch (msel) {
msel              318 drivers/clk/nxp/clk-lpc18xx-cgu.c 		for (i = msel; i <= LPC18XX_PLL0_MSEL_MAX; i++)
msel              325 drivers/clk/nxp/clk-lpc18xx-cgu.c static u32 lpc18xx_pll0_msel2seli(u32 msel)
msel              329 drivers/clk/nxp/clk-lpc18xx-cgu.c 	if (msel > 16384) return 1;
msel              330 drivers/clk/nxp/clk-lpc18xx-cgu.c 	if (msel >  8192) return 2;
msel              331 drivers/clk/nxp/clk-lpc18xx-cgu.c 	if (msel >  2048) return 4;
msel              332 drivers/clk/nxp/clk-lpc18xx-cgu.c 	if (msel >=  501) return 8;
msel              333 drivers/clk/nxp/clk-lpc18xx-cgu.c 	if (msel >=   60) {
msel              334 drivers/clk/nxp/clk-lpc18xx-cgu.c 		tmp = 1024 / (msel + 9);
msel              335 drivers/clk/nxp/clk-lpc18xx-cgu.c 		return ((1024 == (tmp * (msel + 9))) == 0) ? tmp * 4 : (tmp + 1) * 4;
msel              338 drivers/clk/nxp/clk-lpc18xx-cgu.c 	return (msel & 0x3c) + 4;
msel              342 drivers/clk/nxp/clk-lpc18xx-cgu.c static u32 lpc18xx_pll0_msel2selp(u32 msel)
msel              344 drivers/clk/nxp/clk-lpc18xx-cgu.c 	if (msel < 60)
msel              345 drivers/clk/nxp/clk-lpc18xx-cgu.c 		return (msel >> 1) + 1;
msel              354 drivers/clk/nxp/clk-lpc18xx-cgu.c 	u32 ctrl, mdiv, msel, npdiv;
msel              368 drivers/clk/nxp/clk-lpc18xx-cgu.c 	msel = lpc18xx_pll0_mdec2msel(mdiv & LPC18XX_PLL0_MDIV_MDEC_MASK);
msel              369 drivers/clk/nxp/clk-lpc18xx-cgu.c 	if (msel)
msel              370 drivers/clk/nxp/clk-lpc18xx-cgu.c 		return 2 * msel * parent_rate;
msel              458 drivers/clk/nxp/clk-lpc18xx-cgu.c 	u16 msel, nsel, psel;
msel              468 drivers/clk/nxp/clk-lpc18xx-cgu.c 	msel = ((ctrl >> 16) & 0xff) + 1;
msel              472 drivers/clk/nxp/clk-lpc18xx-cgu.c 		return msel * (parent_rate / nsel);
msel              477 drivers/clk/nxp/clk-lpc18xx-cgu.c 	return (msel / (2 * psel)) * (parent_rate / nsel);
msel              278 drivers/fpga/socfpga-a10.c 	u32 msel, stat, mask;
msel              287 drivers/fpga/socfpga-a10.c 	msel = socfpga_a10_fpga_read_stat(priv);
msel              288 drivers/fpga/socfpga-a10.c 	msel &= A10_FPGAMGR_IMGCFG_STAT_F2S_MSEL_MASK;
msel              289 drivers/fpga/socfpga-a10.c 	msel >>= A10_FPGAMGR_IMGCFG_STAT_F2S_MSEL_SHIFT;
msel              290 drivers/fpga/socfpga-a10.c 	if ((msel != 0) && (msel != 1)) {
msel              291 drivers/fpga/socfpga-a10.c 		dev_dbg(&mgr->dev, "Fail: invalid msel=%d\n", msel);
msel              322 drivers/fpga/socfpga.c 	u32 msel;
msel              324 drivers/fpga/socfpga.c 	msel = socfpga_fpga_readl(priv, SOCFPGA_FPGMGR_STAT_OFST);
msel              325 drivers/fpga/socfpga.c 	msel &= SOCFPGA_FPGMGR_STAT_MSEL_MASK;
msel              326 drivers/fpga/socfpga.c 	msel >>= SOCFPGA_FPGMGR_STAT_MSEL_SHIFT;
msel              329 drivers/fpga/socfpga.c 	if ((msel >= ARRAY_SIZE(cfgmgr_modes)) || !cfgmgr_modes[msel].valid)
msel              332 drivers/fpga/socfpga.c 	return msel;
msel               51 drivers/net/dsa/sja1105/sja1105_clocking.c 	u64 msel;
msel              307 drivers/net/dsa/sja1105/sja1105_clocking.c 	sja1105_packing(buf, &cmd->msel,      23, 16, size, op);
msel              589 drivers/net/dsa/sja1105/sja1105_clocking.c 	pll.msel      = 0x1;
msel              384 drivers/pinctrl/sh-pfc/sh_pfc.h #define PINMUX_IPSR_NOGM(ipsr, fn, msel)				\
msel              385 drivers/pinctrl/sh-pfc/sh_pfc.h 	PINMUX_DATA(fn##_MARK, FN_##fn, FN_##msel)
msel              407 drivers/pinctrl/sh-pfc/sh_pfc.h #define PINMUX_IPSR_MSEL(ipsr, fn, msel)				\
msel              408 drivers/pinctrl/sh-pfc/sh_pfc.h 	PINMUX_DATA(fn##_MARK, FN_##msel, FN_##fn, FN_##ipsr)
msel              419 drivers/pinctrl/sh-pfc/sh_pfc.h #define PINMUX_IPSR_PHYS_MSEL(ipsr, fn, psel, msel) \
msel              420 drivers/pinctrl/sh-pfc/sh_pfc.h 	PINMUX_DATA(fn##_MARK, FN_##psel, FN_##msel, FN_##fn, FN_##ipsr)