mscr              867 drivers/edac/cpc925_edac.c 	u32 mscr;
mscr              870 drivers/edac/cpc925_edac.c 	mscr = __raw_readl(pdata->vbase + REG_MSCR_OFFSET);
mscr              871 drivers/edac/cpc925_edac.c 	si = (mscr & MSCR_SI_MASK) >> MSCR_SI_SHIFT;
mscr              873 drivers/edac/cpc925_edac.c 	edac_dbg(0, "Mem Scrub Ctrl Register 0x%x\n", mscr);
mscr              875 drivers/edac/cpc925_edac.c 	if (((mscr & MSCR_SCRUB_MOD_MASK) != MSCR_BACKGR_SCRUB) ||
mscr             1503 drivers/net/ethernet/dlink/dl2k.c 	__u16 mscr;
mscr             1519 drivers/net/ethernet/dlink/dl2k.c 		mscr = mii_read (dev, phy_addr, MII_CTRL1000);
mscr             1521 drivers/net/ethernet/dlink/dl2k.c 		if (mscr & ADVERTISE_1000FULL && mssr & LPA_1000FULL) {
mscr             1525 drivers/net/ethernet/dlink/dl2k.c 		} else if (mscr & ADVERTISE_1000HALF && mssr & LPA_1000HALF) {
mscr             1663 drivers/net/ethernet/dlink/dl2k.c 		mscr = mii_read (dev, phy_addr, MII_CTRL1000);
mscr             1664 drivers/net/ethernet/dlink/dl2k.c 		mscr |= MII_MSCR_CFG_ENABLE;
mscr             1665 drivers/net/ethernet/dlink/dl2k.c 		mscr &= ~MII_MSCR_CFG_VALUE = 0;
mscr              435 drivers/net/phy/marvell.c 	int mscr;
mscr              438 drivers/net/phy/marvell.c 		mscr = MII_88E1121_PHY_MSCR_RX_DELAY |
mscr              441 drivers/net/phy/marvell.c 		mscr = MII_88E1121_PHY_MSCR_RX_DELAY;
mscr              443 drivers/net/phy/marvell.c 		mscr = MII_88E1121_PHY_MSCR_TX_DELAY;
mscr              445 drivers/net/phy/marvell.c 		mscr = 0;
mscr              449 drivers/net/phy/marvell.c 				MII_88E1121_PHY_MSCR_DELAY_MASK, mscr);