mrrs              788 arch/mips/include/asm/octeon/cvmx-dpi-defs.h 		uint64_t mrrs:2;
mrrs              790 arch/mips/include/asm/octeon/cvmx-dpi-defs.h 		uint64_t mrrs:2;
mrrs              820 arch/mips/include/asm/octeon/cvmx-dpi-defs.h 		uint64_t mrrs:2;
mrrs              822 arch/mips/include/asm/octeon/cvmx-dpi-defs.h 		uint64_t mrrs:2;
mrrs              811 arch/mips/include/asm/octeon/cvmx-npei-defs.h 		uint64_t mrrs:3;
mrrs              829 arch/mips/include/asm/octeon/cvmx-npei-defs.h 		uint64_t mrrs:3;
mrrs              145 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h 		__BITFIELD_FIELD(uint32_t mrrs:3,
mrrs               95 arch/mips/include/asm/octeon/cvmx-sli-defs.h 		__BITFIELD_FIELD(uint64_t mrrs:3,
mrrs              405 arch/mips/pci/pcie-octeon.c 		pciercx_cfg030.s.mrrs = MRRS_CN5XXX;
mrrs              408 arch/mips/pci/pcie-octeon.c 		pciercx_cfg030.s.mrrs = MRRS_CN6XXX;
mrrs              440 arch/mips/pci/pcie-octeon.c 		npei_ctl_status2.s.mrrs = MRRS_CN5XXX;
mrrs              458 arch/mips/pci/pcie-octeon.c 		prt_cfg.s.mrrs = MRRS_CN6XXX;
mrrs              464 arch/mips/pci/pcie-octeon.c 		sli_s2m_portx_ctl.s.mrrs = MRRS_CN6XXX;
mrrs             1517 drivers/net/ethernet/broadcom/bnx2x/bnx2x.h 	int			mrrs;
mrrs              117 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c static int mrrs = -1;
mrrs              118 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c module_param(mrrs, int, 0444);
mrrs              119 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c MODULE_PARM_DESC(mrrs, " Force Max Read Req Size (0..3) (for debug)");
mrrs             6905 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c 	if (bp->mrrs == -1)
mrrs             6908 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c 		DP(NETIF_MSG_HW, "force read order to %d\n", bp->mrrs);
mrrs             6909 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c 		r_order = bp->mrrs;
mrrs             12474 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c 	bp->mrrs = mrrs;
mrrs               95 drivers/net/ethernet/cavium/liquidio/cn66xx_device.c 				enum octeon_pcie_mrrs mrrs)
mrrs              103 drivers/net/ethernet/cavium/liquidio/cn66xx_device.c 	if (mrrs == PCIE_MRRS_DEFAULT) {
mrrs              104 drivers/net/ethernet/cavium/liquidio/cn66xx_device.c 		mrrs = ((val & (0x7 << 12)) >> 12);
mrrs              107 drivers/net/ethernet/cavium/liquidio/cn66xx_device.c 		val |= (mrrs << 12); /* Set MRRS */
mrrs              113 drivers/net/ethernet/cavium/liquidio/cn66xx_device.c 	r64 |= mrrs;
mrrs              118 drivers/net/ethernet/cavium/liquidio/cn66xx_device.c 	r64 |= mrrs;
mrrs               73 drivers/net/ethernet/cavium/liquidio/cn66xx_device.h 				enum octeon_pcie_mrrs mrrs);
mrrs             3063 drivers/net/ethernet/jme.c 	pci_read_config_byte(pdev, PCI_DCSR_MRRS, &jme->mrrs);
mrrs             3064 drivers/net/ethernet/jme.c 	jme->mrrs &= PCI_DCSR_MRRS_MASK;
mrrs             3065 drivers/net/ethernet/jme.c 	switch (jme->mrrs) {
mrrs              430 drivers/net/ethernet/jme.h 	u8			mrrs;
mrrs             2619 drivers/pci/probe.c 	int rc, mrrs;
mrrs             2634 drivers/pci/probe.c 	mrrs = pcie_get_mps(dev);
mrrs             2642 drivers/pci/probe.c 	while (mrrs != pcie_get_readrq(dev) && mrrs >= 128) {
mrrs             2643 drivers/pci/probe.c 		rc = pcie_set_readrq(dev, mrrs);
mrrs             2648 drivers/pci/probe.c 		mrrs /= 2;
mrrs             2651 drivers/pci/probe.c 	if (mrrs < 128)