mpll_ss1         4045 drivers/gpu/drm/amd/amdgpu/si_dpm.c 	si_pi->clock_registers.mpll_ss1 = RREG32(MPLL_SS1);
mpll_ss1         4856 drivers/gpu/drm/amd/amdgpu/si_dpm.c 		cpu_to_be32(si_pi->clock_registers.mpll_ss1);
mpll_ss1         5057 drivers/gpu/drm/amd/amdgpu/si_dpm.c 		cpu_to_be32(si_pi->clock_registers.mpll_ss1);
mpll_ss1         5351 drivers/gpu/drm/amd/amdgpu/si_dpm.c 	u32  mpll_ss1 = si_pi->clock_registers.mpll_ss1;
mpll_ss1         5394 drivers/gpu/drm/amd/amdgpu/si_dpm.c 		        mpll_ss1 &= ~CLKV_MASK;
mpll_ss1         5395 drivers/gpu/drm/amd/amdgpu/si_dpm.c 		        mpll_ss1 |= CLKV(clkv);
mpll_ss1         5418 drivers/gpu/drm/amd/amdgpu/si_dpm.c 	mclk->vMPLL_SS = cpu_to_be32(mpll_ss1);
mpll_ss1          361 drivers/gpu/drm/amd/amdgpu/si_dpm.h 	u32 mpll_ss1;
mpll_ss1          507 drivers/gpu/drm/amd/amdgpu/si_dpm.h 	u32 mpll_ss1;
mpll_ss1          919 drivers/gpu/drm/amd/amdgpu/si_dpm.h 	u32 mpll_ss1;
mpll_ss1         1037 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	uint32_t  mpll_ss1 = data->clock_registers.vMPLL_SS1;
mpll_ss1         1090 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 			mpll_ss1 = PHM_SET_FIELD(mpll_ss1, MPLL_SS1, CLKV, clkv);
mpll_ss1         1111 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	mclk->MpllSs1         = mpll_ss1;
mpll_ss1         1061 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	uint32_t  mpll_ss1 = data->clock_registers.vMPLL_SS1;
mpll_ss1         1140 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 			mpll_ss1 = PHM_SET_FIELD(mpll_ss1, MPLL_SS1, CLKV, clkv);
mpll_ss1         1163 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	mclk->MpllSs1         = mpll_ss1;
mpll_ss1          804 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	uint32_t mpll_ss1 = data->clock_registers.vMPLL_SS1;
mpll_ss1          892 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 			mpll_ss1 = PHM_SET_FIELD(mpll_ss1, MPLL_SS1, CLKV, clkv);
mpll_ss1          914 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	mclk->MpllSs1         = mpll_ss1;
mpll_ss1         1893 drivers/gpu/drm/radeon/ci_dpm.c 	pi->clock_registers.mpll_ss1 = RREG32(MPLL_SS1);
mpll_ss1         2802 drivers/gpu/drm/radeon/ci_dpm.c 	u32  mpll_ss1 = pi->clock_registers.mpll_ss1;
mpll_ss1         2845 drivers/gpu/drm/radeon/ci_dpm.c 			mpll_ss1 &= ~CLKV_MASK;
mpll_ss1         2846 drivers/gpu/drm/radeon/ci_dpm.c 			mpll_ss1 |= CLKV(clkv);
mpll_ss1         2869 drivers/gpu/drm/radeon/ci_dpm.c 	mclk->MpllSs1 = mpll_ss1;
mpll_ss1         3084 drivers/gpu/drm/radeon/ci_dpm.c 	table->MemoryACPILevel.MpllSs1 = cpu_to_be32(pi->clock_registers.mpll_ss1);
mpll_ss1          141 drivers/gpu/drm/radeon/ci_dpm.h 	u32 mpll_ss1;
mpll_ss1          493 drivers/gpu/drm/radeon/cypress_dpm.c 	u32 mpll_ss1 = pi->clk_regs.rv770.mpll_ss1;
mpll_ss1          566 drivers/gpu/drm/radeon/cypress_dpm.c 			mpll_ss1 &= ~CLKV_MASK;
mpll_ss1          567 drivers/gpu/drm/radeon/cypress_dpm.c 			mpll_ss1 |= CLKV(clk_v);
mpll_ss1          605 drivers/gpu/drm/radeon/cypress_dpm.c 	mclk->mclk770.vMPLL_SS = cpu_to_be32(mpll_ss1);
mpll_ss1         1258 drivers/gpu/drm/radeon/cypress_dpm.c 		cpu_to_be32(pi->clk_regs.rv770.mpll_ss1);
mpll_ss1         1197 drivers/gpu/drm/radeon/ni_dpm.c 	ni_pi->clock_registers.mpll_ss1 = RREG32(MPLL_SS1);
mpll_ss1         1705 drivers/gpu/drm/radeon/ni_dpm.c 		cpu_to_be32(ni_pi->clock_registers.mpll_ss1);
mpll_ss1         2175 drivers/gpu/drm/radeon/ni_dpm.c 	u32 mpll_ss1 = ni_pi->clock_registers.mpll_ss1;
mpll_ss1         2248 drivers/gpu/drm/radeon/ni_dpm.c 			mpll_ss1 &= ~CLKV_MASK;
mpll_ss1         2249 drivers/gpu/drm/radeon/ni_dpm.c 			mpll_ss1 |= CLKV(clk_v);
mpll_ss1         2288 drivers/gpu/drm/radeon/ni_dpm.c 	mclk->vMPLL_SS = cpu_to_be32(mpll_ss1);
mpll_ss1           43 drivers/gpu/drm/radeon/ni_dpm.h 	u32 mpll_ss1;
mpll_ss1          197 drivers/gpu/drm/radeon/rv740_dpm.c 	u32 mpll_ss1 = pi->clk_regs.rv770.mpll_ss1;
mpll_ss1          257 drivers/gpu/drm/radeon/rv740_dpm.c 			mpll_ss1 &= ~CLKV_MASK;
mpll_ss1          258 drivers/gpu/drm/radeon/rv740_dpm.c 			mpll_ss1 |= CLKV(clk_v);
mpll_ss1          278 drivers/gpu/drm/radeon/rv740_dpm.c 	mclk->mclk770.vMPLL_SS = cpu_to_be32(mpll_ss1);
mpll_ss1          310 drivers/gpu/drm/radeon/rv740_dpm.c 	pi->clk_regs.rv770.mpll_ss1 = RREG32(MPLL_SS1);
mpll_ss1         1044 drivers/gpu/drm/radeon/rv770_dpm.c 		cpu_to_be32(pi->clk_regs.rv770.mpll_ss1);
mpll_ss1           41 drivers/gpu/drm/radeon/rv770_dpm.h 	u32 mpll_ss1;
mpll_ss1         3585 drivers/gpu/drm/radeon/si_dpm.c 	si_pi->clock_registers.mpll_ss1 = RREG32(MPLL_SS1);
mpll_ss1         4392 drivers/gpu/drm/radeon/si_dpm.c 		cpu_to_be32(si_pi->clock_registers.mpll_ss1);
mpll_ss1         4594 drivers/gpu/drm/radeon/si_dpm.c 		cpu_to_be32(si_pi->clock_registers.mpll_ss1);
mpll_ss1         4889 drivers/gpu/drm/radeon/si_dpm.c 	u32  mpll_ss1 = si_pi->clock_registers.mpll_ss1;
mpll_ss1         4932 drivers/gpu/drm/radeon/si_dpm.c 			mpll_ss1 &= ~CLKV_MASK;
mpll_ss1         4933 drivers/gpu/drm/radeon/si_dpm.c 			mpll_ss1 |= CLKV(clkv);
mpll_ss1         4956 drivers/gpu/drm/radeon/si_dpm.c 	mclk->vMPLL_SS = cpu_to_be32(mpll_ss1);
mpll_ss1          103 drivers/gpu/drm/radeon/si_dpm.h 	u32 mpll_ss1;