mpll_param 1089 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c struct atom_mpll_param *mpll_param) mpll_param 1096 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c memset(mpll_param, 0, sizeof(struct atom_mpll_param)); mpll_param 1113 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c mpll_param->clkfrac = le16_to_cpu(args.ulFbDiv.usFbDivFrac); mpll_param 1114 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c mpll_param->clkf = le16_to_cpu(args.ulFbDiv.usFbDiv); mpll_param 1115 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c mpll_param->post_div = args.ucPostDiv; mpll_param 1116 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c mpll_param->dll_speed = args.ucDllSpeed; mpll_param 1117 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c mpll_param->bwcntl = args.ucBWCntl; mpll_param 1118 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c mpll_param->vco_mode = mpll_param 1120 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c mpll_param->yclk_sel = mpll_param 1122 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c mpll_param->qdr = mpll_param 1124 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c mpll_param->half_rate = mpll_param 166 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.h struct atom_mpll_param *mpll_param); mpll_param 5353 drivers/gpu/drm/amd/amdgpu/si_dpm.c struct atom_mpll_param mpll_param; mpll_param 5356 drivers/gpu/drm/amd/amdgpu/si_dpm.c ret = amdgpu_atombios_get_memory_pll_dividers(adev, memory_clock, strobe_mode, &mpll_param); mpll_param 5361 drivers/gpu/drm/amd/amdgpu/si_dpm.c mpll_func_cntl |= BWCTRL(mpll_param.bwcntl); mpll_param 5364 drivers/gpu/drm/amd/amdgpu/si_dpm.c mpll_func_cntl_1 |= CLKF(mpll_param.clkf) | mpll_param 5365 drivers/gpu/drm/amd/amdgpu/si_dpm.c CLKFRAC(mpll_param.clkfrac) | VCO_MODE(mpll_param.vco_mode); mpll_param 5368 drivers/gpu/drm/amd/amdgpu/si_dpm.c mpll_ad_func_cntl |= YCLK_POST_DIV(mpll_param.post_div); mpll_param 5372 drivers/gpu/drm/amd/amdgpu/si_dpm.c mpll_dq_func_cntl |= YCLK_SEL(mpll_param.yclk_sel) | mpll_param 5373 drivers/gpu/drm/amd/amdgpu/si_dpm.c YCLK_POST_DIV(mpll_param.post_div); mpll_param 5403 drivers/gpu/drm/amd/amdgpu/si_dpm.c mclk_pwrmgt_cntl |= DLL_SPEED(mpll_param.dll_speed); mpll_param 250 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c pp_atomctrl_memory_clock_param *mpll_param, mpll_param 265 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c mpll_param->mpll_fb_divider.clk_frac = mpll_param 267 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c mpll_param->mpll_fb_divider.cl_kf = mpll_param 269 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c mpll_param->mpll_post_divider = mpll_param 271 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c mpll_param->vco_mode = mpll_param 274 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c mpll_param->yclk_sel = mpll_param 277 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c mpll_param->qdr = mpll_param 280 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c mpll_param->half_rate = mpll_param 283 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c mpll_param->dll_speed = mpll_param 285 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c mpll_param->bw_ctrl = mpll_param 299 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c uint32_t clock_value, pp_atomctrl_memory_clock_param *mpll_param) mpll_param 312 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c mpll_param->mpll_post_divider = mpll_param 320 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c pp_atomctrl_memory_clock_param_ai *mpll_param) mpll_param 336 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c mpll_param->ulMclk_fcw_int = mpll_param 338 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c mpll_param->ulMclk_fcw_frac = mpll_param 340 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c mpll_param->ulClock = mpll_param 342 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c mpll_param->ulPostDiv = mpll_parameters.ulClock.ucPostDiv; mpll_param 299 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h extern int atomctrl_get_memory_pll_dividers_si(struct pp_hwmgr *hwmgr, uint32_t clock_value, pp_atomctrl_memory_clock_param *mpll_param, bool strobe_mode); mpll_param 305 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h uint32_t clock_value, pp_atomctrl_memory_clock_param *mpll_param); mpll_param 307 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h uint32_t clock_value, pp_atomctrl_memory_clock_param_ai *mpll_param); mpll_param 1040 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c pp_atomctrl_memory_clock_param mpll_param; mpll_param 1044 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c memory_clock, &mpll_param, strobe_mode); mpll_param 1048 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c mpll_func_cntl = PHM_SET_FIELD(mpll_func_cntl, MPLL_FUNC_CNTL, BWCTRL, mpll_param.bw_ctrl); mpll_param 1051 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c MPLL_FUNC_CNTL_1, CLKF, mpll_param.mpll_fb_divider.cl_kf); mpll_param 1053 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c MPLL_FUNC_CNTL_1, CLKFRAC, mpll_param.mpll_fb_divider.clk_frac); mpll_param 1055 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c MPLL_FUNC_CNTL_1, VCO_MODE, mpll_param.vco_mode); mpll_param 1058 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c MPLL_AD_FUNC_CNTL, YCLK_POST_DIV, mpll_param.mpll_post_divider); mpll_param 1062 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c MPLL_DQ_FUNC_CNTL, YCLK_SEL, mpll_param.yclk_sel); mpll_param 1064 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c MPLL_DQ_FUNC_CNTL, YCLK_POST_DIV, mpll_param.mpll_post_divider); mpll_param 1075 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c if (1 == mpll_param.qdr) mpll_param 1076 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c freq_nom = memory_clock * 4 * (1 << mpll_param.mpll_post_divider); mpll_param 1078 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c freq_nom = memory_clock * 2 * (1 << mpll_param.mpll_post_divider); mpll_param 1096 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c MCLK_PWRMGT_CNTL, DLL_SPEED, mpll_param.dll_speed); mpll_param 1064 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c pp_atomctrl_memory_clock_param mpll_param; mpll_param 1068 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c memory_clock, &mpll_param, strobe_mode); mpll_param 1073 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c mpll_func_cntl = PHM_SET_FIELD(mpll_func_cntl, MPLL_FUNC_CNTL, BWCTRL, mpll_param.bw_ctrl); mpll_param 1077 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c MPLL_FUNC_CNTL_1, CLKF, mpll_param.mpll_fb_divider.cl_kf); mpll_param 1079 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c MPLL_FUNC_CNTL_1, CLKFRAC, mpll_param.mpll_fb_divider.clk_frac); mpll_param 1081 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c MPLL_FUNC_CNTL_1, VCO_MODE, mpll_param.vco_mode); mpll_param 1085 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c MPLL_AD_FUNC_CNTL, YCLK_POST_DIV, mpll_param.mpll_post_divider); mpll_param 1090 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c MPLL_DQ_FUNC_CNTL, YCLK_SEL, mpll_param.yclk_sel); mpll_param 1092 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c MPLL_DQ_FUNC_CNTL, YCLK_POST_DIV, mpll_param.mpll_post_divider); mpll_param 1118 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c if (1 == mpll_param.qdr) mpll_param 1119 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c freq_nom = memory_clock * 4 * (1 << mpll_param.mpll_post_divider); mpll_param 1121 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c freq_nom = memory_clock * 2 * (1 << mpll_param.mpll_post_divider); mpll_param 1147 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c MCLK_PWRMGT_CNTL, DLL_SPEED, mpll_param.dll_speed); mpll_param 807 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c pp_atomctrl_memory_clock_param mpll_param; mpll_param 811 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c memory_clock, &mpll_param, strobe_mode); mpll_param 819 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c mpll_param.bw_ctrl); mpll_param 824 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c mpll_param.mpll_fb_divider.cl_kf); mpll_param 827 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c mpll_param.mpll_fb_divider.clk_frac); mpll_param 830 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c mpll_param.vco_mode); mpll_param 835 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c mpll_param.mpll_post_divider); mpll_param 841 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c mpll_param.yclk_sel); mpll_param 844 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c mpll_param.mpll_post_divider); mpll_param 870 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c if (1 == mpll_param.qdr) mpll_param 871 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c freq_nom = memory_clock * 4 * (1 << mpll_param.mpll_post_divider); mpll_param 873 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c freq_nom = memory_clock * 2 * (1 << mpll_param.mpll_post_divider); mpll_param 899 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c MCLK_PWRMGT_CNTL, DLL_SPEED, mpll_param.dll_speed); mpll_param 963 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c struct pp_atomctrl_memory_clock_param_ai mpll_param; mpll_param 966 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c clock, &mpll_param), mpll_param 970 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c mem_level->MclkFrequency = (uint32_t)mpll_param.ulClock; mpll_param 971 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c mem_level->Fcw_int = (uint16_t)mpll_param.ulMclk_fcw_int; mpll_param 972 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c mem_level->Fcw_frac = (uint16_t)mpll_param.ulMclk_fcw_frac; mpll_param 973 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c mem_level->Postdiv = (uint8_t)mpll_param.ulPostDiv; mpll_param 2804 drivers/gpu/drm/radeon/ci_dpm.c struct atom_mpll_param mpll_param; mpll_param 2807 drivers/gpu/drm/radeon/ci_dpm.c ret = radeon_atom_get_memory_pll_dividers(rdev, memory_clock, strobe_mode, &mpll_param); mpll_param 2812 drivers/gpu/drm/radeon/ci_dpm.c mpll_func_cntl |= BWCTRL(mpll_param.bwcntl); mpll_param 2815 drivers/gpu/drm/radeon/ci_dpm.c mpll_func_cntl_1 |= CLKF(mpll_param.clkf) | mpll_param 2816 drivers/gpu/drm/radeon/ci_dpm.c CLKFRAC(mpll_param.clkfrac) | VCO_MODE(mpll_param.vco_mode); mpll_param 2819 drivers/gpu/drm/radeon/ci_dpm.c mpll_ad_func_cntl |= YCLK_POST_DIV(mpll_param.post_div); mpll_param 2823 drivers/gpu/drm/radeon/ci_dpm.c mpll_dq_func_cntl |= YCLK_SEL(mpll_param.yclk_sel) | mpll_param 2824 drivers/gpu/drm/radeon/ci_dpm.c YCLK_POST_DIV(mpll_param.post_div); mpll_param 2833 drivers/gpu/drm/radeon/ci_dpm.c if (mpll_param.qdr == 1) mpll_param 2834 drivers/gpu/drm/radeon/ci_dpm.c freq_nom = memory_clock * 4 * (1 << mpll_param.post_div); mpll_param 2836 drivers/gpu/drm/radeon/ci_dpm.c freq_nom = memory_clock * 2 * (1 << mpll_param.post_div); mpll_param 2854 drivers/gpu/drm/radeon/ci_dpm.c mclk_pwrmgt_cntl |= DLL_SPEED(mpll_param.dll_speed); mpll_param 298 drivers/gpu/drm/radeon/radeon.h struct atom_mpll_param *mpll_param); mpll_param 2957 drivers/gpu/drm/radeon/radeon_atombios.c struct atom_mpll_param *mpll_param) mpll_param 2964 drivers/gpu/drm/radeon/radeon_atombios.c memset(mpll_param, 0, sizeof(struct atom_mpll_param)); mpll_param 2981 drivers/gpu/drm/radeon/radeon_atombios.c mpll_param->clkfrac = le16_to_cpu(args.ulFbDiv.usFbDivFrac); mpll_param 2982 drivers/gpu/drm/radeon/radeon_atombios.c mpll_param->clkf = le16_to_cpu(args.ulFbDiv.usFbDiv); mpll_param 2983 drivers/gpu/drm/radeon/radeon_atombios.c mpll_param->post_div = args.ucPostDiv; mpll_param 2984 drivers/gpu/drm/radeon/radeon_atombios.c mpll_param->dll_speed = args.ucDllSpeed; mpll_param 2985 drivers/gpu/drm/radeon/radeon_atombios.c mpll_param->bwcntl = args.ucBWCntl; mpll_param 2986 drivers/gpu/drm/radeon/radeon_atombios.c mpll_param->vco_mode = mpll_param 2988 drivers/gpu/drm/radeon/radeon_atombios.c mpll_param->yclk_sel = mpll_param 2990 drivers/gpu/drm/radeon/radeon_atombios.c mpll_param->qdr = mpll_param 2992 drivers/gpu/drm/radeon/radeon_atombios.c mpll_param->half_rate = mpll_param 4891 drivers/gpu/drm/radeon/si_dpm.c struct atom_mpll_param mpll_param; mpll_param 4894 drivers/gpu/drm/radeon/si_dpm.c ret = radeon_atom_get_memory_pll_dividers(rdev, memory_clock, strobe_mode, &mpll_param); mpll_param 4899 drivers/gpu/drm/radeon/si_dpm.c mpll_func_cntl |= BWCTRL(mpll_param.bwcntl); mpll_param 4902 drivers/gpu/drm/radeon/si_dpm.c mpll_func_cntl_1 |= CLKF(mpll_param.clkf) | mpll_param 4903 drivers/gpu/drm/radeon/si_dpm.c CLKFRAC(mpll_param.clkfrac) | VCO_MODE(mpll_param.vco_mode); mpll_param 4906 drivers/gpu/drm/radeon/si_dpm.c mpll_ad_func_cntl |= YCLK_POST_DIV(mpll_param.post_div); mpll_param 4910 drivers/gpu/drm/radeon/si_dpm.c mpll_dq_func_cntl |= YCLK_SEL(mpll_param.yclk_sel) | mpll_param 4911 drivers/gpu/drm/radeon/si_dpm.c YCLK_POST_DIV(mpll_param.post_div); mpll_param 4941 drivers/gpu/drm/radeon/si_dpm.c mclk_pwrmgt_cntl |= DLL_SPEED(mpll_param.dll_speed);