mpll_func_cntl_3  127 drivers/gpu/drm/radeon/rv730_dpm.c 	u32 mpll_func_cntl_3 = pi->clk_regs.rv730.mpll_func_cntl3;
mpll_func_cntl_3  158 drivers/gpu/drm/radeon/rv730_dpm.c 	mpll_func_cntl_3 &= ~MPLL_FB_DIV_MASK;
mpll_func_cntl_3  159 drivers/gpu/drm/radeon/rv730_dpm.c 	mpll_func_cntl_3 |= MPLL_FB_DIV(dividers.fb_div);
mpll_func_cntl_3  161 drivers/gpu/drm/radeon/rv730_dpm.c 		mpll_func_cntl_3 |= MPLL_DITHEN;
mpll_func_cntl_3  163 drivers/gpu/drm/radeon/rv730_dpm.c 		mpll_func_cntl_3 &= ~MPLL_DITHEN;
mpll_func_cntl_3  190 drivers/gpu/drm/radeon/rv730_dpm.c 	mclk->mclk730.vMPLL_FUNC_CNTL3 = cpu_to_be32(mpll_func_cntl_3);
mpll_func_cntl_3  234 drivers/gpu/drm/radeon/rv730_dpm.c 	u32 mpll_func_cntl_3 = 0;
mpll_func_cntl_3  259 drivers/gpu/drm/radeon/rv730_dpm.c 	mpll_func_cntl_3 = pi->clk_regs.rv730.mpll_func_cntl3;
mpll_func_cntl_3  298 drivers/gpu/drm/radeon/rv730_dpm.c 	table->ACPIState.levels[0].mclk.mclk730.vMPLL_FUNC_CNTL3 = cpu_to_be32(mpll_func_cntl_3);