mpll_func_cntl_1 4043 drivers/gpu/drm/amd/amdgpu/si_dpm.c 	si_pi->clock_registers.mpll_func_cntl_1 = RREG32(MPLL_FUNC_CNTL_1);
mpll_func_cntl_1 4852 drivers/gpu/drm/amd/amdgpu/si_dpm.c 		cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_1);
mpll_func_cntl_1 4966 drivers/gpu/drm/amd/amdgpu/si_dpm.c 	u32 mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1;
mpll_func_cntl_1 5053 drivers/gpu/drm/amd/amdgpu/si_dpm.c 		cpu_to_be32(mpll_func_cntl_1);
mpll_func_cntl_1 5349 drivers/gpu/drm/amd/amdgpu/si_dpm.c 	u32  mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1;
mpll_func_cntl_1 5363 drivers/gpu/drm/amd/amdgpu/si_dpm.c 	mpll_func_cntl_1 &= ~(CLKF_MASK | CLKFRAC_MASK | VCO_MODE_MASK);
mpll_func_cntl_1 5364 drivers/gpu/drm/amd/amdgpu/si_dpm.c 	mpll_func_cntl_1 |= CLKF(mpll_param.clkf) |
mpll_func_cntl_1 5412 drivers/gpu/drm/amd/amdgpu/si_dpm.c 	mclk->vMPLL_FUNC_CNTL_1 = cpu_to_be32(mpll_func_cntl_1);
mpll_func_cntl_1  917 drivers/gpu/drm/amd/amdgpu/si_dpm.h 	u32 mpll_func_cntl_1;
mpll_func_cntl_1 1035 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	uint32_t  mpll_func_cntl_1 = data->clock_registers.vMPLL_FUNC_CNTL_1;
mpll_func_cntl_1 1050 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	mpll_func_cntl_1  = PHM_SET_FIELD(mpll_func_cntl_1,
mpll_func_cntl_1 1052 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	mpll_func_cntl_1  = PHM_SET_FIELD(mpll_func_cntl_1,
mpll_func_cntl_1 1054 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	mpll_func_cntl_1  = PHM_SET_FIELD(mpll_func_cntl_1,
mpll_func_cntl_1 1105 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	mclk->MpllFuncCntl_1  = mpll_func_cntl_1;
mpll_func_cntl_1 1059 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	uint32_t  mpll_func_cntl_1 = data->clock_registers.vMPLL_FUNC_CNTL_1;
mpll_func_cntl_1 1076 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	mpll_func_cntl_1  = PHM_SET_FIELD(mpll_func_cntl_1,
mpll_func_cntl_1 1078 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	mpll_func_cntl_1  = PHM_SET_FIELD(mpll_func_cntl_1,
mpll_func_cntl_1 1080 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	mpll_func_cntl_1  = PHM_SET_FIELD(mpll_func_cntl_1,
mpll_func_cntl_1 1157 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	mclk->MpllFuncCntl_1  = mpll_func_cntl_1;
mpll_func_cntl_1  802 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	uint32_t mpll_func_cntl_1 = data->clock_registers.vMPLL_FUNC_CNTL_1;
mpll_func_cntl_1  822 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	mpll_func_cntl_1  = PHM_SET_FIELD(mpll_func_cntl_1,
mpll_func_cntl_1  825 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	mpll_func_cntl_1  = PHM_SET_FIELD(mpll_func_cntl_1,
mpll_func_cntl_1  828 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	mpll_func_cntl_1  = PHM_SET_FIELD(mpll_func_cntl_1,
mpll_func_cntl_1  908 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	mclk->MpllFuncCntl_1  = mpll_func_cntl_1;
mpll_func_cntl_1 1891 drivers/gpu/drm/radeon/ci_dpm.c 	pi->clock_registers.mpll_func_cntl_1 = RREG32(MPLL_FUNC_CNTL_1);
mpll_func_cntl_1 2800 drivers/gpu/drm/radeon/ci_dpm.c 	u32  mpll_func_cntl_1 = pi->clock_registers.mpll_func_cntl_1;
mpll_func_cntl_1 2814 drivers/gpu/drm/radeon/ci_dpm.c 	mpll_func_cntl_1 &= ~(CLKF_MASK | CLKFRAC_MASK | VCO_MODE_MASK);
mpll_func_cntl_1 2815 drivers/gpu/drm/radeon/ci_dpm.c 	mpll_func_cntl_1 |= CLKF(mpll_param.clkf) |
mpll_func_cntl_1 2863 drivers/gpu/drm/radeon/ci_dpm.c 	mclk->MpllFuncCntl_1 = mpll_func_cntl_1;
mpll_func_cntl_1 3081 drivers/gpu/drm/radeon/ci_dpm.c 		cpu_to_be32(pi->clock_registers.mpll_func_cntl_1);
mpll_func_cntl_1  139 drivers/gpu/drm/radeon/ci_dpm.h 	u32 mpll_func_cntl_1;
mpll_func_cntl_1 3583 drivers/gpu/drm/radeon/si_dpm.c 	si_pi->clock_registers.mpll_func_cntl_1 = RREG32(MPLL_FUNC_CNTL_1);
mpll_func_cntl_1 4388 drivers/gpu/drm/radeon/si_dpm.c 		cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_1);
mpll_func_cntl_1 4504 drivers/gpu/drm/radeon/si_dpm.c 	u32 mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1;
mpll_func_cntl_1 4590 drivers/gpu/drm/radeon/si_dpm.c 		cpu_to_be32(mpll_func_cntl_1);
mpll_func_cntl_1 4887 drivers/gpu/drm/radeon/si_dpm.c 	u32  mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1;
mpll_func_cntl_1 4901 drivers/gpu/drm/radeon/si_dpm.c 	mpll_func_cntl_1 &= ~(CLKF_MASK | CLKFRAC_MASK | VCO_MODE_MASK);
mpll_func_cntl_1 4902 drivers/gpu/drm/radeon/si_dpm.c 	mpll_func_cntl_1 |= CLKF(mpll_param.clkf) |
mpll_func_cntl_1 4950 drivers/gpu/drm/radeon/si_dpm.c 	mclk->vMPLL_FUNC_CNTL_1 = cpu_to_be32(mpll_func_cntl_1);
mpll_func_cntl_1  101 drivers/gpu/drm/radeon/si_dpm.h 	u32 mpll_func_cntl_1;