mpll_func_cntl   4042 drivers/gpu/drm/amd/amdgpu/si_dpm.c 	si_pi->clock_registers.mpll_func_cntl = RREG32(MPLL_FUNC_CNTL);
mpll_func_cntl   4850 drivers/gpu/drm/amd/amdgpu/si_dpm.c 		cpu_to_be32(si_pi->clock_registers.mpll_func_cntl);
mpll_func_cntl   4965 drivers/gpu/drm/amd/amdgpu/si_dpm.c 	u32 mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl;
mpll_func_cntl   5051 drivers/gpu/drm/amd/amdgpu/si_dpm.c 		cpu_to_be32(mpll_func_cntl);
mpll_func_cntl   5348 drivers/gpu/drm/amd/amdgpu/si_dpm.c 	u32  mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl;
mpll_func_cntl   5360 drivers/gpu/drm/amd/amdgpu/si_dpm.c 	mpll_func_cntl &= ~BWCTRL_MASK;
mpll_func_cntl   5361 drivers/gpu/drm/amd/amdgpu/si_dpm.c 	mpll_func_cntl |= BWCTRL(mpll_param.bwcntl);
mpll_func_cntl   5411 drivers/gpu/drm/amd/amdgpu/si_dpm.c 	mclk->vMPLL_FUNC_CNTL = cpu_to_be32(mpll_func_cntl);
mpll_func_cntl    519 drivers/gpu/drm/amd/amdgpu/si_dpm.h 	u32 mpll_func_cntl;
mpll_func_cntl    916 drivers/gpu/drm/amd/amdgpu/si_dpm.h 	u32 mpll_func_cntl;
mpll_func_cntl   1034 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	uint32_t  mpll_func_cntl = data->clock_registers.vMPLL_FUNC_CNTL;
mpll_func_cntl   1048 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	mpll_func_cntl = PHM_SET_FIELD(mpll_func_cntl, MPLL_FUNC_CNTL, BWCTRL, mpll_param.bw_ctrl);
mpll_func_cntl   1104 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	mclk->MpllFuncCntl    = mpll_func_cntl;
mpll_func_cntl   1058 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	uint32_t  mpll_func_cntl = data->clock_registers.vMPLL_FUNC_CNTL;
mpll_func_cntl   1073 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	mpll_func_cntl = PHM_SET_FIELD(mpll_func_cntl, MPLL_FUNC_CNTL, BWCTRL, mpll_param.bw_ctrl);
mpll_func_cntl   1156 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	mclk->MpllFuncCntl    = mpll_func_cntl;
mpll_func_cntl    801 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	uint32_t mpll_func_cntl = data->clock_registers.vMPLL_FUNC_CNTL;
mpll_func_cntl    818 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	mpll_func_cntl = PHM_SET_FIELD(mpll_func_cntl, MPLL_FUNC_CNTL, BWCTRL,
mpll_func_cntl    907 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	mclk->MpllFuncCntl    = mpll_func_cntl;
mpll_func_cntl   1890 drivers/gpu/drm/radeon/ci_dpm.c 	pi->clock_registers.mpll_func_cntl = RREG32(MPLL_FUNC_CNTL);
mpll_func_cntl   2799 drivers/gpu/drm/radeon/ci_dpm.c 	u32  mpll_func_cntl = pi->clock_registers.mpll_func_cntl;
mpll_func_cntl   2811 drivers/gpu/drm/radeon/ci_dpm.c 	mpll_func_cntl &= ~BWCTRL_MASK;
mpll_func_cntl   2812 drivers/gpu/drm/radeon/ci_dpm.c 	mpll_func_cntl |= BWCTRL(mpll_param.bwcntl);
mpll_func_cntl   2862 drivers/gpu/drm/radeon/ci_dpm.c 	mclk->MpllFuncCntl = mpll_func_cntl;
mpll_func_cntl   3079 drivers/gpu/drm/radeon/ci_dpm.c 		cpu_to_be32(pi->clock_registers.mpll_func_cntl);
mpll_func_cntl    138 drivers/gpu/drm/radeon/ci_dpm.h 	u32 mpll_func_cntl;
mpll_func_cntl    125 drivers/gpu/drm/radeon/rv730_dpm.c 	u32 mpll_func_cntl = pi->clk_regs.rv730.mpll_func_cntl;
mpll_func_cntl    149 drivers/gpu/drm/radeon/rv730_dpm.c 		mpll_func_cntl |= MPLL_DIVEN;
mpll_func_cntl    151 drivers/gpu/drm/radeon/rv730_dpm.c 		mpll_func_cntl &= ~MPLL_DIVEN;
mpll_func_cntl    153 drivers/gpu/drm/radeon/rv730_dpm.c 	mpll_func_cntl &= ~(MPLL_REF_DIV_MASK | MPLL_HILEN_MASK | MPLL_LOLEN_MASK);
mpll_func_cntl    154 drivers/gpu/drm/radeon/rv730_dpm.c 	mpll_func_cntl |= MPLL_REF_DIV(dividers.ref_div);
mpll_func_cntl    155 drivers/gpu/drm/radeon/rv730_dpm.c 	mpll_func_cntl |= MPLL_HILEN((dividers.post_div >> 4) & 0xf);
mpll_func_cntl    156 drivers/gpu/drm/radeon/rv730_dpm.c 	mpll_func_cntl |= MPLL_LOLEN(dividers.post_div & 0xf);
mpll_func_cntl    188 drivers/gpu/drm/radeon/rv730_dpm.c 	mclk->mclk730.vMPLL_FUNC_CNTL = cpu_to_be32(mpll_func_cntl);
mpll_func_cntl    216 drivers/gpu/drm/radeon/rv730_dpm.c 	pi->clk_regs.rv730.mpll_func_cntl =
mpll_func_cntl    232 drivers/gpu/drm/radeon/rv730_dpm.c 	u32 mpll_func_cntl = 0;
mpll_func_cntl    257 drivers/gpu/drm/radeon/rv730_dpm.c 	mpll_func_cntl = pi->clk_regs.rv730.mpll_func_cntl;
mpll_func_cntl    261 drivers/gpu/drm/radeon/rv730_dpm.c 	mpll_func_cntl |= MPLL_RESET | MPLL_BYPASS_EN;
mpll_func_cntl    262 drivers/gpu/drm/radeon/rv730_dpm.c 	mpll_func_cntl &= ~MPLL_SLEEP;
mpll_func_cntl    296 drivers/gpu/drm/radeon/rv730_dpm.c 	table->ACPIState.levels[0].mclk.mclk730.vMPLL_FUNC_CNTL = cpu_to_be32(mpll_func_cntl);
mpll_func_cntl    327 drivers/gpu/drm/radeon/rv730_dpm.c 		cpu_to_be32(pi->clk_regs.rv730.mpll_func_cntl);
mpll_func_cntl     53 drivers/gpu/drm/radeon/rv770_dpm.h 	u32 mpll_func_cntl;
mpll_func_cntl   3582 drivers/gpu/drm/radeon/si_dpm.c 	si_pi->clock_registers.mpll_func_cntl = RREG32(MPLL_FUNC_CNTL);
mpll_func_cntl   4386 drivers/gpu/drm/radeon/si_dpm.c 		cpu_to_be32(si_pi->clock_registers.mpll_func_cntl);
mpll_func_cntl   4503 drivers/gpu/drm/radeon/si_dpm.c 	u32 mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl;
mpll_func_cntl   4588 drivers/gpu/drm/radeon/si_dpm.c 		cpu_to_be32(mpll_func_cntl);
mpll_func_cntl   4886 drivers/gpu/drm/radeon/si_dpm.c 	u32  mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl;
mpll_func_cntl   4898 drivers/gpu/drm/radeon/si_dpm.c 	mpll_func_cntl &= ~BWCTRL_MASK;
mpll_func_cntl   4899 drivers/gpu/drm/radeon/si_dpm.c 	mpll_func_cntl |= BWCTRL(mpll_param.bwcntl);
mpll_func_cntl   4949 drivers/gpu/drm/radeon/si_dpm.c 	mclk->vMPLL_FUNC_CNTL = cpu_to_be32(mpll_func_cntl);
mpll_func_cntl    100 drivers/gpu/drm/radeon/si_dpm.h 	u32 mpll_func_cntl;