mpcc_inst         528 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	secondary_pipe->plane_res.mpcc_inst = pool->dpps[secondary_pipe->pipe_idx]->inst;
mpcc_inst        1219 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 			split_pipe->plane_res.mpcc_inst = pool->dpps[i]->inst;
mpcc_inst        1624 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 				pipe_ctx->plane_res.mpcc_inst = pool->dpps[i]->inst;
mpcc_inst        1895 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 			pipe_ctx->plane_res.mpcc_inst = pool->dpps[tg_inst]->inst;
mpcc_inst         995 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		opp->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true;
mpcc_inst        1151 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		pipe_ctx->plane_res.mpcc_inst = dpp->inst;
mpcc_inst        1158 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		dc->res_pool->opps[i]->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true;
mpcc_inst        2871 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c static struct hubp *get_hubp_by_inst(struct resource_pool *res_pool, int mpcc_inst)
mpcc_inst        2876 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		if (res_pool->hubps[i]->inst == mpcc_inst)
mpcc_inst        2888 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	int mpcc_inst;
mpcc_inst        2897 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	for (mpcc_inst = 0; mpcc_inst < MAX_PIPES; mpcc_inst++) {
mpcc_inst        2898 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		if (pipe_ctx->stream_res.opp->mpcc_disconnect_pending[mpcc_inst]) {
mpcc_inst        2899 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 			struct hubp *hubp = get_hubp_by_inst(res_pool, mpcc_inst);
mpcc_inst        2901 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 			res_pool->mpc->funcs->wait_for_idle(res_pool->mpc, mpcc_inst);
mpcc_inst        2902 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 			pipe_ctx->stream_res.opp->mpcc_disconnect_pending[mpcc_inst] = false;
mpcc_inst         327 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c static void mpc1_init_mpcc(struct mpcc *mpcc, int mpcc_inst)
mpcc_inst         329 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c 	mpcc->mpcc_id = mpcc_inst;
mpcc_inst         433 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c 		int mpcc_inst,
mpcc_inst         438 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c 	REG_GET(MPCC_OPP_ID[mpcc_inst], MPCC_OPP_ID, &s->opp_id);
mpcc_inst         439 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c 	REG_GET(MPCC_TOP_SEL[mpcc_inst], MPCC_TOP_SEL, &s->dpp_id);
mpcc_inst         440 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c 	REG_GET(MPCC_BOT_SEL[mpcc_inst], MPCC_BOT_SEL, &s->bot_mpcc_id);
mpcc_inst         441 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c 	REG_GET_4(MPCC_CONTROL[mpcc_inst], MPCC_MODE, &s->mode,
mpcc_inst         445 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c 	REG_GET_2(MPCC_STATUS[mpcc_inst], MPCC_IDLE, &s->idle,
mpcc_inst         192 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h 		int mpcc_inst,
mpcc_inst        1113 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c 	idle_pipe->plane_res.mpcc_inst = pool->dpps[idle_pipe->pipe_idx]->inst;
mpcc_inst        2066 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 		pipe_ctx->plane_res.mpcc_inst = dpp->inst;
mpcc_inst        2076 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 		dc->res_pool->opps[i]->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true;
mpcc_inst         468 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c static void mpc2_init_mpcc(struct mpcc *mpcc, int mpcc_inst)
mpcc_inst         470 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c 	mpcc->mpcc_id = mpcc_inst;
mpcc_inst        1738 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	next_odm_pipe->plane_res.mpcc_inst = pool->dpps[next_odm_pipe->pipe_idx]->inst;
mpcc_inst        1818 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	secondary_pipe->plane_res.mpcc_inst = pool->dpps[secondary_pipe->pipe_idx]->inst;
mpcc_inst        2956 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	idle_pipe->plane_res.mpcc_inst = pool->dpps[idle_pipe->pipe_idx]->inst;
mpcc_inst         264 drivers/gpu/drm/amd/display/dc/inc/core_types.h 	uint8_t mpcc_inst;
mpcc_inst         150 drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h 			int mpcc_inst,