mpcc_in_use_mask  100 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c 	ASSERT(!(mpc10->mpcc_in_use_mask & 1 << id));
mpcc_in_use_mask  190 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c 	ASSERT(!(mpc10->mpcc_in_use_mask & 1 << mpcc_id));
mpcc_in_use_mask  249 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c 	mpc10->mpcc_in_use_mask |= 1 << mpcc_id;
mpcc_in_use_mask  316 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c 		mpc10->mpcc_in_use_mask &= ~(1 << mpcc_id);
mpcc_in_use_mask  352 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c 	mpc10->mpcc_in_use_mask = 0;
mpcc_in_use_mask  412 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c 				mpc10->mpcc_in_use_mask |= 1 << mpcc_id;
mpcc_in_use_mask  485 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c 	mpc10->mpcc_in_use_mask = 0;
mpcc_in_use_mask  121 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h 	int mpcc_in_use_mask;
mpcc_in_use_mask  435 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c 	ASSERT(!(mpc20->mpcc_in_use_mask & 1 << id));
mpcc_in_use_mask  532 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c 	mpc20->mpcc_in_use_mask = 0;
mpcc_in_use_mask  240 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h 	int mpcc_in_use_mask;