mpcc_id 65 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c hubp->mpcc_id = 0xf; mpcc_id 1268 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c hubp1->base.mpcc_id = 0xf; mpcc_id 1152 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c hubp->mpcc_id = dpp->inst; mpcc_id 2188 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c int mpcc_id; mpcc_id 2234 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c mpcc_id = hubp->inst; mpcc_id 2238 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c mpc->funcs->update_blending(mpc, &blnd_cfg, mpcc_id); mpcc_id 2243 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c new_mpcc = mpc->funcs->get_mpcc_for_dpp(mpc_tree_params, mpcc_id); mpcc_id 2250 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c dc->res_pool->mpc, mpcc_id); mpcc_id 2259 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c mpcc_id); mpcc_id 2264 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c hubp->mpcc_id = mpcc_id; mpcc_id 42 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c int mpcc_id) mpcc_id 54 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c REG_SET(MPCC_BG_R_CR[mpcc_id], 0, mpcc_id 56 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c REG_SET(MPCC_BG_G_Y[mpcc_id], 0, mpcc_id 58 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c REG_SET(MPCC_BG_B_CB[mpcc_id], 0, mpcc_id 65 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c int mpcc_id) mpcc_id 68 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c struct mpcc *mpcc = mpc1_get_mpcc(mpc, mpcc_id); mpcc_id 70 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c REG_UPDATE_5(MPCC_CONTROL[mpcc_id], mpcc_id 77 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c mpc1_set_bg_color(mpc, &blnd_cfg->black_color, mpcc_id); mpcc_id 84 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c int mpcc_id) mpcc_id 88 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c REG_UPDATE_6(MPCC_SM_CONTROL[mpcc_id], mpcc_id 106 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c struct mpcc *mpc1_get_mpcc(struct mpc *mpc, int mpcc_id) mpcc_id 110 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c ASSERT(mpcc_id < mpc10->num_mpcc); mpcc_id 111 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c return &(mpc->mpcc_array[mpcc_id]); mpcc_id 126 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c bool mpc1_is_mpcc_idle(struct mpc *mpc, int mpcc_id) mpcc_id 133 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c REG_GET(MPCC_TOP_SEL[mpcc_id], MPCC_TOP_SEL, &top_sel); mpcc_id 134 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c REG_GET(MPCC_OPP_ID[mpcc_id], MPCC_OPP_ID, &opp_id); mpcc_id 135 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c REG_GET(MPCC_STATUS[mpcc_id], MPCC_IDLE, &idle); mpcc_id 142 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c void mpc1_assert_mpcc_idle_before_connect(struct mpc *mpc, int mpcc_id) mpcc_id 147 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c REG_GET(MPCC_TOP_SEL[mpcc_id], mpcc_id 151 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c REG_GET_2(MPCC_STATUS[mpcc_id], mpcc_id 183 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c int mpcc_id) mpcc_id 189 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c ASSERT(mpcc_id < mpc10->num_mpcc); mpcc_id 190 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c ASSERT(!(mpc10->mpcc_in_use_mask & 1 << mpcc_id)); mpcc_id 203 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c new_mpcc = mpc1_get_mpcc(mpc, mpcc_id); mpcc_id 209 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c REG_SET(MPCC_BOT_SEL[mpcc_id], 0, MPCC_BOT_SEL, insert_above_mpcc->mpcc_id); mpcc_id 210 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c REG_UPDATE(MPCC_CONTROL[mpcc_id], MPCC_MODE, MPCC_BLEND_MODE_TOP_BOT_BLENDING); mpcc_id 213 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c REG_SET(MPCC_BOT_SEL[mpcc_id], 0, MPCC_BOT_SEL, 0xf); mpcc_id 214 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c REG_UPDATE(MPCC_CONTROL[mpcc_id], MPCC_MODE, MPCC_BLEND_MODE_TOP_LAYER_ONLY); mpcc_id 216 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c REG_SET(MPCC_TOP_SEL[mpcc_id], 0, MPCC_TOP_SEL, dpp_id); mpcc_id 217 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c REG_SET(MPCC_OPP_ID[mpcc_id], 0, MPCC_OPP_ID, tree->opp_id); mpcc_id 223 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c REG_UPDATE(MUX[tree->opp_id], MPC_OUT_MUX, mpcc_id); mpcc_id 231 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c REG_SET(MPCC_BOT_SEL[temp_mpcc->mpcc_id], 0, MPCC_BOT_SEL, mpcc_id); mpcc_id 234 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c REG_UPDATE(MPCC_CONTROL[temp_mpcc->mpcc_id], mpcc_id 240 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c mpc->funcs->update_blending(mpc, blnd_cfg, mpcc_id); mpcc_id 245 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c mpc1_update_stereo_mix(mpc, sm_cfg, mpcc_id); mpcc_id 249 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c mpc10->mpcc_in_use_mask |= 1 << mpcc_id; mpcc_id 271 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c int mpcc_id = mpcc_to_remove->mpcc_id; mpcc_id 279 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c REG_UPDATE(MUX[tree->opp_id], MPC_OUT_MUX, tree->opp_list->mpcc_id); mpcc_id 297 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c REG_SET(MPCC_BOT_SEL[temp_mpcc->mpcc_id], 0, mpcc_id 298 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c MPCC_BOT_SEL, mpcc_to_remove->mpcc_bot->mpcc_id); mpcc_id 301 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c REG_SET(MPCC_BOT_SEL[temp_mpcc->mpcc_id], 0, mpcc_id 303 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c REG_UPDATE(MPCC_CONTROL[temp_mpcc->mpcc_id], mpcc_id 311 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c REG_SET(MPCC_TOP_SEL[mpcc_id], 0, MPCC_TOP_SEL, 0xf); mpcc_id 312 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c REG_SET(MPCC_BOT_SEL[mpcc_id], 0, MPCC_BOT_SEL, 0xf); mpcc_id 313 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c REG_SET(MPCC_OPP_ID[mpcc_id], 0, MPCC_OPP_ID, 0xf); mpcc_id 316 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c mpc10->mpcc_in_use_mask &= ~(1 << mpcc_id); mpcc_id 321 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c REG_SET(MPCC_TOP_SEL[mpcc_id], 0, MPCC_TOP_SEL, 0xf); mpcc_id 322 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c REG_SET(MPCC_BOT_SEL[mpcc_id], 0, MPCC_BOT_SEL, 0xf); mpcc_id 323 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c REG_SET(MPCC_OPP_ID[mpcc_id], 0, MPCC_OPP_ID, 0xf); mpcc_id 329 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c mpcc->mpcc_id = mpcc_inst; mpcc_id 349 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c int mpcc_id; mpcc_id 353 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c for (mpcc_id = 0; mpcc_id < mpc10->num_mpcc; mpcc_id++) { mpcc_id 354 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c REG_SET(MPCC_TOP_SEL[mpcc_id], 0, MPCC_TOP_SEL, 0xf); mpcc_id 355 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c REG_SET(MPCC_BOT_SEL[mpcc_id], 0, MPCC_BOT_SEL, 0xf); mpcc_id 356 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c REG_SET(MPCC_OPP_ID[mpcc_id], 0, MPCC_OPP_ID, 0xf); mpcc_id 358 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c mpc1_init_mpcc(&(mpc->mpcc_array[mpcc_id]), mpcc_id); mpcc_id 367 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c void mpc1_mpc_init_single_inst(struct mpc *mpc, unsigned int mpcc_id) mpcc_id 372 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c REG_GET(MPCC_OPP_ID[mpcc_id], MPCC_OPP_ID, &opp_id); mpcc_id 374 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c REG_SET(MPCC_TOP_SEL[mpcc_id], 0, MPCC_TOP_SEL, 0xf); mpcc_id 375 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c REG_SET(MPCC_BOT_SEL[mpcc_id], 0, MPCC_BOT_SEL, 0xf); mpcc_id 376 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c REG_SET(MPCC_OPP_ID[mpcc_id], 0, MPCC_OPP_ID, 0xf); mpcc_id 378 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c mpc1_init_mpcc(&(mpc->mpcc_array[mpcc_id]), mpcc_id); mpcc_id 395 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c int mpcc_id; mpcc_id 401 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c for (mpcc_id = 0; mpcc_id < mpc10->num_mpcc; mpcc_id++) { mpcc_id 402 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c REG_GET(MPCC_OPP_ID[mpcc_id], MPCC_OPP_ID, &opp_id); mpcc_id 403 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c REG_GET(MPCC_TOP_SEL[mpcc_id], MPCC_TOP_SEL, &top_sel); mpcc_id 404 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c REG_GET(MPCC_BOT_SEL[mpcc_id], MPCC_BOT_SEL, &bot_sel); mpcc_id 406 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c if (bot_sel == mpcc_id) mpcc_id 410 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c mpcc = mpc1_get_mpcc(mpc, mpcc_id); mpcc_id 412 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c mpc10->mpcc_in_use_mask |= 1 << mpcc_id; mpcc_id 414 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c if (out_mux == mpcc_id) mpcc_id 142 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h int mpcc_id); mpcc_id 154 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h unsigned int mpcc_id); mpcc_id 168 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h int mpcc_id); mpcc_id 172 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h int mpcc_id); mpcc_id 176 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h int mpcc_id); mpcc_id 184 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h int mpcc_id); mpcc_id 933 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c hubp->mpcc_id = 0xf; mpcc_id 1287 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c hubp2->base.mpcc_id = 0xf; mpcc_id 631 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c int mpcc_id = pipe_ctx->plane_res.hubp->inst; mpcc_id 634 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c mpc->funcs->power_on_mpc_mem_pwr(mpc, mpcc_id, true); mpcc_id 654 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c int mpcc_id = pipe_ctx->plane_res.hubp->inst; mpcc_id 665 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c mpc->funcs->power_on_mpc_mem_pwr(mpc, mpcc_id, true); mpcc_id 685 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c mpc->funcs->set_output_gamma(mpc, mpcc_id, params); mpcc_id 1729 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c int mpcc_id; mpcc_id 1771 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c mpcc_id = hubp->inst; mpcc_id 1775 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c mpc->funcs->update_blending(mpc, &blnd_cfg, mpcc_id); mpcc_id 1780 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c new_mpcc = mpc->funcs->get_mpcc_for_dpp(mpc_tree_params, mpcc_id); mpcc_id 1787 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c dc->res_pool->mpc, mpcc_id); mpcc_id 1796 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c mpcc_id); mpcc_id 1800 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c hubp->mpcc_id = mpcc_id; mpcc_id 2067 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c hubp->mpcc_id = dpp->inst; mpcc_id 48 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c int mpcc_id) mpcc_id 52 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c struct mpcc *mpcc = mpc1_get_mpcc(mpc, mpcc_id); mpcc_id 54 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c REG_UPDATE_7(MPCC_CONTROL[mpcc_id], mpcc_id 63 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c REG_SET(MPCC_TOP_GAIN[mpcc_id], 0, MPCC_TOP_GAIN, blnd_cfg->top_gain); mpcc_id 64 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c REG_SET(MPCC_BOT_GAIN_INSIDE[mpcc_id], 0, MPCC_BOT_GAIN_INSIDE, blnd_cfg->bottom_inside_gain); mpcc_id 65 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c REG_SET(MPCC_BOT_GAIN_OUTSIDE[mpcc_id], 0, MPCC_BOT_GAIN_OUTSIDE, blnd_cfg->bottom_outside_gain); mpcc_id 67 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c mpc1_set_bg_color(mpc, &blnd_cfg->black_color, mpcc_id); mpcc_id 237 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c struct mpc *mpc, int mpcc_id, mpcc_id 242 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c REG_SET(MPCC_MEM_PWR_CTRL[mpcc_id], 0, mpcc_id 248 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c struct mpc *mpc, int mpcc_id, mpcc_id 253 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c REG_UPDATE_2(MPCC_OGAM_LUT_RAM_CONTROL[mpcc_id], mpcc_id 257 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c REG_SET(MPCC_OGAM_LUT_INDEX[mpcc_id], 0, MPCC_OGAM_LUT_INDEX, 0); mpcc_id 260 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c static enum dc_lut_mode mpc20_get_ogam_current(struct mpc *mpc, int mpcc_id) mpcc_id 266 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c REG_GET(MPCC_OGAM_LUT_RAM_CONTROL[mpcc_id], mpcc_id 286 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c static void mpc2_program_lutb(struct mpc *mpc, int mpcc_id, mpcc_id 294 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c gam_regs.start_cntl_b = REG(MPCC_OGAM_RAMB_START_CNTL_B[mpcc_id]); mpcc_id 295 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c gam_regs.start_cntl_g = REG(MPCC_OGAM_RAMB_START_CNTL_G[mpcc_id]); mpcc_id 296 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c gam_regs.start_cntl_r = REG(MPCC_OGAM_RAMB_START_CNTL_R[mpcc_id]); mpcc_id 297 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c gam_regs.start_slope_cntl_b = REG(MPCC_OGAM_RAMB_SLOPE_CNTL_B[mpcc_id]); mpcc_id 298 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c gam_regs.start_slope_cntl_g = REG(MPCC_OGAM_RAMB_SLOPE_CNTL_G[mpcc_id]); mpcc_id 299 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c gam_regs.start_slope_cntl_r = REG(MPCC_OGAM_RAMB_SLOPE_CNTL_R[mpcc_id]); mpcc_id 300 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c gam_regs.start_end_cntl1_b = REG(MPCC_OGAM_RAMB_END_CNTL1_B[mpcc_id]); mpcc_id 301 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c gam_regs.start_end_cntl2_b = REG(MPCC_OGAM_RAMB_END_CNTL2_B[mpcc_id]); mpcc_id 302 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c gam_regs.start_end_cntl1_g = REG(MPCC_OGAM_RAMB_END_CNTL1_G[mpcc_id]); mpcc_id 303 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c gam_regs.start_end_cntl2_g = REG(MPCC_OGAM_RAMB_END_CNTL2_G[mpcc_id]); mpcc_id 304 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c gam_regs.start_end_cntl1_r = REG(MPCC_OGAM_RAMB_END_CNTL1_R[mpcc_id]); mpcc_id 305 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c gam_regs.start_end_cntl2_r = REG(MPCC_OGAM_RAMB_END_CNTL2_R[mpcc_id]); mpcc_id 306 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c gam_regs.region_start = REG(MPCC_OGAM_RAMB_REGION_0_1[mpcc_id]); mpcc_id 307 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c gam_regs.region_end = REG(MPCC_OGAM_RAMB_REGION_32_33[mpcc_id]); mpcc_id 313 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c static void mpc2_program_luta(struct mpc *mpc, int mpcc_id, mpcc_id 321 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c gam_regs.start_cntl_b = REG(MPCC_OGAM_RAMA_START_CNTL_B[mpcc_id]); mpcc_id 322 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c gam_regs.start_cntl_g = REG(MPCC_OGAM_RAMA_START_CNTL_G[mpcc_id]); mpcc_id 323 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c gam_regs.start_cntl_r = REG(MPCC_OGAM_RAMA_START_CNTL_R[mpcc_id]); mpcc_id 324 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c gam_regs.start_slope_cntl_b = REG(MPCC_OGAM_RAMA_SLOPE_CNTL_B[mpcc_id]); mpcc_id 325 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c gam_regs.start_slope_cntl_g = REG(MPCC_OGAM_RAMA_SLOPE_CNTL_G[mpcc_id]); mpcc_id 326 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c gam_regs.start_slope_cntl_r = REG(MPCC_OGAM_RAMA_SLOPE_CNTL_R[mpcc_id]); mpcc_id 327 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c gam_regs.start_end_cntl1_b = REG(MPCC_OGAM_RAMA_END_CNTL1_B[mpcc_id]); mpcc_id 328 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c gam_regs.start_end_cntl2_b = REG(MPCC_OGAM_RAMA_END_CNTL2_B[mpcc_id]); mpcc_id 329 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c gam_regs.start_end_cntl1_g = REG(MPCC_OGAM_RAMA_END_CNTL1_G[mpcc_id]); mpcc_id 330 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c gam_regs.start_end_cntl2_g = REG(MPCC_OGAM_RAMA_END_CNTL2_G[mpcc_id]); mpcc_id 331 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c gam_regs.start_end_cntl1_r = REG(MPCC_OGAM_RAMA_END_CNTL1_R[mpcc_id]); mpcc_id 332 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c gam_regs.start_end_cntl2_r = REG(MPCC_OGAM_RAMA_END_CNTL2_R[mpcc_id]); mpcc_id 333 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c gam_regs.region_start = REG(MPCC_OGAM_RAMA_REGION_0_1[mpcc_id]); mpcc_id 334 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c gam_regs.region_end = REG(MPCC_OGAM_RAMA_REGION_32_33[mpcc_id]); mpcc_id 341 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c struct mpc *mpc, int mpcc_id, mpcc_id 349 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c REG_SET(MPCC_OGAM_LUT_DATA[mpcc_id], 0, MPCC_OGAM_LUT_DATA, rgb[i].red_reg); mpcc_id 350 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c REG_SET(MPCC_OGAM_LUT_DATA[mpcc_id], 0, MPCC_OGAM_LUT_DATA, rgb[i].green_reg); mpcc_id 351 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c REG_SET(MPCC_OGAM_LUT_DATA[mpcc_id], 0, MPCC_OGAM_LUT_DATA, rgb[i].blue_reg); mpcc_id 353 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c REG_SET(MPCC_OGAM_LUT_DATA[mpcc_id], 0, mpcc_id 355 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c REG_SET(MPCC_OGAM_LUT_DATA[mpcc_id], 0, mpcc_id 357 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c REG_SET(MPCC_OGAM_LUT_DATA[mpcc_id], 0, mpcc_id 366 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c int mpcc_id, enum dc_lut_mode current_mode, mpcc_id 372 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c REG_SET(MPCC_OGAM_MODE[mpcc_id], 0, MPCC_OGAM_MODE, 0); mpcc_id 385 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c REG_SET(MPCC_OGAM_MODE[mpcc_id], 0, MPCC_OGAM_MODE, mpcc_id 391 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c int mpcc_id, mpcc_id 399 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c REG_SET(MPCC_OGAM_MODE[mpcc_id], 0, MPCC_OGAM_MODE, 0); mpcc_id 404 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c REG_SET(MPCC_OGAM_MODE[mpcc_id], 0, MPCC_OGAM_MODE, 0); mpcc_id 408 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c current_mode = mpc20_get_ogam_current(mpc, mpcc_id); mpcc_id 414 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c mpc20_power_on_ogam_lut(mpc, mpcc_id, true); mpcc_id 415 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c mpc20_configure_ogam_lut(mpc, mpcc_id, next_mode == LUT_RAM_A ? true:false); mpcc_id 418 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c mpc2_program_luta(mpc, mpcc_id, params); mpcc_id 420 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c mpc2_program_lutb(mpc, mpcc_id, params); mpcc_id 422 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c apply_DEDCN20_305_wa(mpc, mpcc_id, current_mode, next_mode); mpcc_id 425 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c mpc, mpcc_id, params->rgb_resulted, params->hw_points_num); mpcc_id 427 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c REG_SET(MPCC_OGAM_MODE[mpcc_id], 0, MPCC_OGAM_MODE, mpcc_id 445 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c void mpc2_assert_mpcc_idle_before_connect(struct mpc *mpc, int mpcc_id) mpcc_id 450 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c REG_GET(MPCC_TOP_SEL[mpcc_id], mpcc_id 453 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c REG_GET_3(MPCC_STATUS[mpcc_id], mpcc_id 470 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c mpcc->mpcc_id = mpcc_inst; mpcc_id 257 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h int mpcc_id); mpcc_id 283 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h int mpcc_id, mpcc_id 287 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h void mpc2_assert_mpcc_idle_before_connect(struct mpc *mpc, int mpcc_id); mpcc_id 288 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h void mpc20_power_on_ogam_lut(struct mpc *mpc, int mpcc_id, bool power_on); mpcc_id 241 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c hubp21->base.mpcc_id = 0xf; mpcc_id 63 drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h int mpcc_id; mpcc_id 109 drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h int mpcc_id; /* MPCC physical instance */ mpcc_id 176 drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h int mpcc_id); mpcc_id 204 drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h unsigned int mpcc_id); mpcc_id 219 drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h int mpcc_id); mpcc_id 227 drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h void (*assert_mpcc_idle_before_connect)(struct mpc *mpc, int mpcc_id); mpcc_id 255 drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h int mpcc_id, mpcc_id 259 drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h int mpcc_id,