mpc_shift          37 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c 	mpc10->mpc_shift->field_name, mpc10->mpc_mask->field_name
mpc_shift         471 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c 	const struct dcn_mpc_shift *mpc_shift,
mpc_shift         482 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c 	mpc10->mpc_shift = mpc_shift;
mpc_shift         124 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h 	const struct dcn_mpc_shift *mpc_shift;
mpc_shift         131 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h 	const struct dcn_mpc_shift *mpc_shift,
mpc_shift         411 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c static const struct dcn_mpc_shift mpc_shift = {
mpc_shift         693 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c 			&mpc_shift,
mpc_shift          41 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c 	mpc20->mpc_shift->field_name, mpc20->mpc_mask->field_name
mpc_shift         148 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c 	ocsc_regs.shifts.csc_c11 = mpc20->mpc_shift->MPC_OCSC_C11_A;
mpc_shift         150 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c 	ocsc_regs.shifts.csc_c12 = mpc20->mpc_shift->MPC_OCSC_C12_A;
mpc_shift         188 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c 	ocsc_regs.shifts.csc_c11 = mpc20->mpc_shift->MPC_OCSC_C11_A;
mpc_shift         190 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c 	ocsc_regs.shifts.csc_c12 = mpc20->mpc_shift->MPC_OCSC_C12_A;
mpc_shift         214 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c 	reg->shifts.exp_region0_lut_offset = mpc20->mpc_shift->MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET;
mpc_shift         216 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c 	reg->shifts.exp_region0_num_segments = mpc20->mpc_shift->MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS;
mpc_shift         218 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c 	reg->shifts.exp_region1_lut_offset = mpc20->mpc_shift->MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET;
mpc_shift         220 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c 	reg->shifts.exp_region1_num_segments = mpc20->mpc_shift->MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS;
mpc_shift         222 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c 	reg->shifts.field_region_end = mpc20->mpc_shift->MPCC_OGAM_RAMA_EXP_REGION_END_B;
mpc_shift         224 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c 	reg->shifts.field_region_end_slope = mpc20->mpc_shift->MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B;
mpc_shift         226 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c 	reg->shifts.field_region_end_base = mpc20->mpc_shift->MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B;
mpc_shift         228 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c 	reg->shifts.field_region_linear_slope = mpc20->mpc_shift->MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B;
mpc_shift         230 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c 	reg->shifts.exp_region_start = mpc20->mpc_shift->MPCC_OGAM_RAMA_EXP_REGION_START_B;
mpc_shift         232 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c 	reg->shifts.exp_resion_start_segment = mpc20->mpc_shift->MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B;
mpc_shift         518 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c 	const struct dcn20_mpc_shift *mpc_shift,
mpc_shift         529 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c 	mpc20->mpc_shift = mpc_shift;
mpc_shift         243 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h 	const struct dcn20_mpc_shift *mpc_shift;
mpc_shift         250 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h 	const struct dcn20_mpc_shift *mpc_shift,
mpc_shift         751 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c static const struct dcn20_mpc_shift mpc_shift = {
mpc_shift        1084 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 			&mpc_shift,
mpc_shift         460 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c static const struct dcn20_mpc_shift mpc_shift = {
mpc_shift        1240 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c 			&mpc_shift,