mpc_mask 37 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c mpc10->mpc_shift->field_name, mpc10->mpc_mask->field_name mpc_mask 472 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c const struct dcn_mpc_mask *mpc_mask, mpc_mask 483 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c mpc10->mpc_mask = mpc_mask; mpc_mask 125 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h const struct dcn_mpc_mask *mpc_mask; mpc_mask 132 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h const struct dcn_mpc_mask *mpc_mask, mpc_mask 415 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c static const struct dcn_mpc_mask mpc_mask = { mpc_mask 694 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c &mpc_mask, mpc_mask 41 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c mpc20->mpc_shift->field_name, mpc20->mpc_mask->field_name mpc_mask 149 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c ocsc_regs.masks.csc_c11 = mpc20->mpc_mask->MPC_OCSC_C11_A; mpc_mask 151 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c ocsc_regs.masks.csc_c12 = mpc20->mpc_mask->MPC_OCSC_C12_A; mpc_mask 189 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c ocsc_regs.masks.csc_c11 = mpc20->mpc_mask->MPC_OCSC_C11_A; mpc_mask 191 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c ocsc_regs.masks.csc_c12 = mpc20->mpc_mask->MPC_OCSC_C12_A; mpc_mask 215 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c reg->masks.exp_region0_lut_offset = mpc20->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET; mpc_mask 217 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c reg->masks.exp_region0_num_segments = mpc20->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS; mpc_mask 219 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c reg->masks.exp_region1_lut_offset = mpc20->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET; mpc_mask 221 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c reg->masks.exp_region1_num_segments = mpc20->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS; mpc_mask 223 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c reg->masks.field_region_end = mpc20->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION_END_B; mpc_mask 225 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c reg->masks.field_region_end_slope = mpc20->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B; mpc_mask 227 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c reg->masks.field_region_end_base = mpc20->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B; mpc_mask 229 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c reg->masks.field_region_linear_slope = mpc20->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B; mpc_mask 231 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c reg->masks.exp_region_start = mpc20->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION_START_B; mpc_mask 233 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c reg->masks.exp_resion_start_segment = mpc20->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B; mpc_mask 519 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c const struct dcn20_mpc_mask *mpc_mask, mpc_mask 530 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c mpc20->mpc_mask = mpc_mask; mpc_mask 244 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h const struct dcn20_mpc_mask *mpc_mask; mpc_mask 251 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h const struct dcn20_mpc_mask *mpc_mask, mpc_mask 755 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c static const struct dcn20_mpc_mask mpc_mask = { mpc_mask 1085 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c &mpc_mask, mpc_mask 464 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c static const struct dcn20_mpc_mask mpc_mask = { mpc_mask 1241 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c &mpc_mask,