mpc20 34 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c mpc20->mpc_regs->reg mpc20 37 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c mpc20->base.ctx mpc20 41 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c mpc20->mpc_shift->field_name, mpc20->mpc_mask->field_name mpc20 50 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c struct dcn20_mpc *mpc20 = TO_DCN20_MPC(mpc); mpc20 76 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c struct dcn20_mpc *mpc20 = TO_DCN20_MPC(mpc); mpc20 114 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c struct dcn20_mpc *mpc20 = TO_DCN20_MPC(mpc); mpc20 135 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c struct dcn20_mpc *mpc20 = TO_DCN20_MPC(mpc); mpc20 148 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c ocsc_regs.shifts.csc_c11 = mpc20->mpc_shift->MPC_OCSC_C11_A; mpc20 149 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c ocsc_regs.masks.csc_c11 = mpc20->mpc_mask->MPC_OCSC_C11_A; mpc20 150 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c ocsc_regs.shifts.csc_c12 = mpc20->mpc_shift->MPC_OCSC_C12_A; mpc20 151 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c ocsc_regs.masks.csc_c12 = mpc20->mpc_mask->MPC_OCSC_C12_A; mpc20 161 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c mpc20->base.ctx, mpc20 172 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c struct dcn20_mpc *mpc20 = TO_DCN20_MPC(mpc); mpc20 188 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c ocsc_regs.shifts.csc_c11 = mpc20->mpc_shift->MPC_OCSC_C11_A; mpc20 189 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c ocsc_regs.masks.csc_c11 = mpc20->mpc_mask->MPC_OCSC_C11_A; mpc20 190 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c ocsc_regs.shifts.csc_c12 = mpc20->mpc_shift->MPC_OCSC_C12_A; mpc20 191 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c ocsc_regs.masks.csc_c12 = mpc20->mpc_mask->MPC_OCSC_C12_A; mpc20 203 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c mpc20->base.ctx, mpc20 212 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c struct dcn20_mpc *mpc20 = TO_DCN20_MPC(mpc); mpc20 214 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c reg->shifts.exp_region0_lut_offset = mpc20->mpc_shift->MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET; mpc20 215 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c reg->masks.exp_region0_lut_offset = mpc20->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET; mpc20 216 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c reg->shifts.exp_region0_num_segments = mpc20->mpc_shift->MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS; mpc20 217 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c reg->masks.exp_region0_num_segments = mpc20->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS; mpc20 218 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c reg->shifts.exp_region1_lut_offset = mpc20->mpc_shift->MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET; mpc20 219 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c reg->masks.exp_region1_lut_offset = mpc20->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET; mpc20 220 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c reg->shifts.exp_region1_num_segments = mpc20->mpc_shift->MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS; mpc20 221 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c reg->masks.exp_region1_num_segments = mpc20->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS; mpc20 222 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c reg->shifts.field_region_end = mpc20->mpc_shift->MPCC_OGAM_RAMA_EXP_REGION_END_B; mpc20 223 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c reg->masks.field_region_end = mpc20->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION_END_B; mpc20 224 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c reg->shifts.field_region_end_slope = mpc20->mpc_shift->MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B; mpc20 225 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c reg->masks.field_region_end_slope = mpc20->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B; mpc20 226 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c reg->shifts.field_region_end_base = mpc20->mpc_shift->MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B; mpc20 227 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c reg->masks.field_region_end_base = mpc20->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B; mpc20 228 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c reg->shifts.field_region_linear_slope = mpc20->mpc_shift->MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B; mpc20 229 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c reg->masks.field_region_linear_slope = mpc20->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B; mpc20 230 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c reg->shifts.exp_region_start = mpc20->mpc_shift->MPCC_OGAM_RAMA_EXP_REGION_START_B; mpc20 231 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c reg->masks.exp_region_start = mpc20->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION_START_B; mpc20 232 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c reg->shifts.exp_resion_start_segment = mpc20->mpc_shift->MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B; mpc20 233 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c reg->masks.exp_resion_start_segment = mpc20->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B; mpc20 240 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c struct dcn20_mpc *mpc20 = TO_DCN20_MPC(mpc); mpc20 251 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c struct dcn20_mpc *mpc20 = TO_DCN20_MPC(mpc); mpc20 264 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c struct dcn20_mpc *mpc20 = TO_DCN20_MPC(mpc); mpc20 289 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c struct dcn20_mpc *mpc20 = TO_DCN20_MPC(mpc); mpc20 309 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c cm_helper_program_xfer_func(mpc20->base.ctx, params, &gam_regs); mpc20 316 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c struct dcn20_mpc *mpc20 = TO_DCN20_MPC(mpc); mpc20 336 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c cm_helper_program_xfer_func(mpc20->base.ctx, params, &gam_regs); mpc20 346 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c struct dcn20_mpc *mpc20 = TO_DCN20_MPC(mpc); mpc20 369 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c struct dcn20_mpc *mpc20 = TO_DCN20_MPC(mpc); mpc20 396 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c struct dcn20_mpc *mpc20 = TO_DCN20_MPC(mpc); mpc20 432 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c struct dcn20_mpc *mpc20 = TO_DCN20_MPC(mpc); mpc20 435 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c ASSERT(!(mpc20->mpcc_in_use_mask & 1 << id)); mpc20 447 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c struct dcn20_mpc *mpc20 = TO_DCN20_MPC(mpc); mpc20 515 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c void dcn20_mpc_construct(struct dcn20_mpc *mpc20, mpc20 524 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c mpc20->base.ctx = ctx; mpc20 526 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c mpc20->base.funcs = &dcn20_mpc_funcs; mpc20 528 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c mpc20->mpc_regs = mpc_regs; mpc20 529 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c mpc20->mpc_shift = mpc_shift; mpc20 530 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c mpc20->mpc_mask = mpc_mask; mpc20 532 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c mpc20->mpcc_in_use_mask = 0; mpc20 533 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c mpc20->num_mpcc = num_mpcc; mpc20 536 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c mpc2_init_mpcc(&mpc20->base.mpcc_array[i], i); mpc20 1076 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c struct dcn20_mpc *mpc20 = kzalloc(sizeof(struct dcn20_mpc), mpc20 1079 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c if (!mpc20) mpc20 1082 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c dcn20_mpc_construct(mpc20, ctx, mpc20 1088 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c return &mpc20->base; mpc20 1232 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c struct dcn20_mpc *mpc20 = kzalloc(sizeof(struct dcn20_mpc), mpc20 1235 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c if (!mpc20) mpc20 1238 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c dcn20_mpc_construct(mpc20, ctx, mpc20 1244 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c return &mpc20->base;