mpc10              30 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c 	mpc10->mpc_regs->reg
mpc10              33 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c 	mpc10->base.ctx
mpc10              37 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c 	mpc10->mpc_shift->field_name, mpc10->mpc_mask->field_name
mpc10              44 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c 	struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc);
mpc10              67 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c 	struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc);
mpc10              86 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c 	struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc);
mpc10              98 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c 	struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc);
mpc10             100 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c 	ASSERT(!(mpc10->mpcc_in_use_mask & 1 << id));
mpc10             108 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c 	struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc);
mpc10             110 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c 	ASSERT(mpcc_id < mpc10->num_mpcc);
mpc10             128 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c 	struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc);
mpc10             144 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c 	struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc);
mpc10             185 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c 	struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc);
mpc10             189 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c 	ASSERT(mpcc_id < mpc10->num_mpcc);
mpc10             190 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c 	ASSERT(!(mpc10->mpcc_in_use_mask & 1 << mpcc_id));
mpc10             249 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c 	mpc10->mpcc_in_use_mask |= 1 << mpcc_id;
mpc10             269 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c 	struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc);
mpc10             316 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c 		mpc10->mpcc_in_use_mask &= ~(1 << mpcc_id);
mpc10             348 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c 	struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc);
mpc10             352 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c 	mpc10->mpcc_in_use_mask = 0;
mpc10             353 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c 	for (mpcc_id = 0; mpcc_id < mpc10->num_mpcc; mpcc_id++) {
mpc10             369 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c 	struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc);
mpc10             389 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c 	struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc);
mpc10             401 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c 		for (mpcc_id = 0; mpcc_id < mpc10->num_mpcc; mpcc_id++) {
mpc10             412 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c 				mpc10->mpcc_in_use_mask |= 1 << mpcc_id;
mpc10             416 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c 				if (bot_sel != 0xf && bot_sel < mpc10->num_mpcc) {
mpc10             436 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c 	struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc);
mpc10             468 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c void dcn10_mpc_construct(struct dcn10_mpc *mpc10,
mpc10             477 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c 	mpc10->base.ctx = ctx;
mpc10             479 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c 	mpc10->base.funcs = &dcn10_mpc_funcs;
mpc10             481 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c 	mpc10->mpc_regs = mpc_regs;
mpc10             482 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c 	mpc10->mpc_shift = mpc_shift;
mpc10             483 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c 	mpc10->mpc_mask = mpc_mask;
mpc10             485 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c 	mpc10->mpcc_in_use_mask = 0;
mpc10             486 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c 	mpc10->num_mpcc = num_mpcc;
mpc10             489 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c 		mpc1_init_mpcc(&mpc10->base.mpcc_array[i], i);
mpc10             685 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c 	struct dcn10_mpc *mpc10 = kzalloc(sizeof(struct dcn10_mpc),
mpc10             688 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c 	if (!mpc10)
mpc10             691 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c 	dcn10_mpc_construct(mpc10, ctx,
mpc10             697 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c 	return &mpc10->base;