movi               46 arch/csky/abiv1/inc/abi/entry.h 	movi	r13, \epc_inc
movi              175 arch/csky/abiv1/inc/abi/entry.h 	movi	r6, 0
movi               30 arch/csky/abiv2/inc/abi/entry.h 	movi	tls, \epc_inc
movi              185 arch/csky/abiv2/inc/abi/entry.h 	movi	r6, 7
movi              200 arch/csky/abiv2/inc/abi/entry.h 	movi	r6, 0
movi              209 arch/csky/abiv2/inc/abi/entry.h 	movi    r7, 0x00000006
movi              212 arch/csky/abiv2/inc/abi/entry.h 	movi    r7, 0x00001006
movi              235 arch/csky/abiv2/inc/abi/entry.h 	movi    r6, 0
movi              120 arch/xtensa/include/asm/asm-uaccess.h 	movi	\at, __XTENSA_UL_CONST(TASK_SIZE)
movi               52 arch/xtensa/include/asm/asmmacro.h 		movi	\at, ((\size + \incr - 1) / (\incr))
movi               58 arch/xtensa/include/asm/cacheasm.h 	movi	\ar, 0
movi               48 arch/xtensa/include/asm/initialize_mmu.h 	movi	a3, 0x25	/* For SMP/MX -- internal for writeback,
movi               52 arch/xtensa/include/asm/initialize_mmu.h 	movi	a3, 0x29	/* non-MX -- Most cores use Std Memory
movi               70 arch/xtensa/include/asm/initialize_mmu.h 	movi	a1, 0
movi               75 arch/xtensa/include/asm/initialize_mmu.h 1:	movi	a2, 0x10000000
movi               85 arch/xtensa/include/asm/initialize_mmu.h 	movi	a2, TEMP_MAPPING_VADDR | XCHAL_SPANNING_WAY
movi              111 arch/xtensa/include/asm/initialize_mmu.h 2:	movi	a4, 0x20000000
movi              120 arch/xtensa/include/asm/initialize_mmu.h 	movi	a6, 0x01000000
movi              125 arch/xtensa/include/asm/initialize_mmu.h 	movi	a5, XCHAL_KSEG_CACHED_VADDR + XCHAL_KSEG_TLB_WAY
movi              126 arch/xtensa/include/asm/initialize_mmu.h 	movi	a4, XCHAL_KSEG_PADDR + CA_WRITEBACK
movi              130 arch/xtensa/include/asm/initialize_mmu.h 	movi	a5, XCHAL_KSEG_BYPASS_VADDR + XCHAL_KSEG_TLB_WAY
movi              131 arch/xtensa/include/asm/initialize_mmu.h 	movi	a4, XCHAL_KSEG_PADDR + CA_BYPASS
movi              136 arch/xtensa/include/asm/initialize_mmu.h 	movi	a5, XCHAL_KSEG_CACHED_VADDR + 0x10000000 + XCHAL_KSEG_TLB_WAY
movi              137 arch/xtensa/include/asm/initialize_mmu.h 	movi	a4, XCHAL_KSEG_PADDR + 0x10000000 + CA_WRITEBACK
movi              141 arch/xtensa/include/asm/initialize_mmu.h 	movi	a5, XCHAL_KSEG_BYPASS_VADDR + 0x10000000 + XCHAL_KSEG_TLB_WAY
movi              142 arch/xtensa/include/asm/initialize_mmu.h 	movi	a4, XCHAL_KSEG_PADDR + 0x10000000 + CA_BYPASS
movi              147 arch/xtensa/include/asm/initialize_mmu.h 	movi	a5, XCHAL_KIO_CACHED_VADDR + XCHAL_KIO_TLB_WAY
movi              148 arch/xtensa/include/asm/initialize_mmu.h 	movi	a4, XCHAL_KIO_DEFAULT_PADDR + CA_WRITEBACK
movi              152 arch/xtensa/include/asm/initialize_mmu.h 	movi	a5, XCHAL_KIO_BYPASS_VADDR + XCHAL_KIO_TLB_WAY
movi              153 arch/xtensa/include/asm/initialize_mmu.h 	movi	a4, XCHAL_KIO_DEFAULT_PADDR + CA_BYPASS
movi              160 arch/xtensa/include/asm/initialize_mmu.h 	movi	a4, 1f
movi              169 arch/xtensa/include/asm/initialize_mmu.h 	movi	a0, 0
movi              195 arch/xtensa/include/asm/initialize_mmu.h 	movi	a3, .Lattribute_table
movi              196 arch/xtensa/include/asm/initialize_mmu.h 	movi	a4, CONFIG_MEMMAP_CACHEATTR
movi              197 arch/xtensa/include/asm/initialize_mmu.h 	movi	a5, 1
movi              198 arch/xtensa/include/asm/initialize_mmu.h 	movi	a6, XCHAL_MPU_ENTRIES
movi              199 arch/xtensa/include/asm/initialize_mmu.h 	movi	a10, 0x20000000
movi              200 arch/xtensa/include/asm/initialize_mmu.h 	movi	a11, -1
movi              216 arch/xtensa/include/asm/initialize_mmu.h 	movi	a5, XCHAL_SPANNING_WAY
movi              217 arch/xtensa/include/asm/initialize_mmu.h 	movi	a6, ~_PAGE_ATTRIB_MASK
movi              218 arch/xtensa/include/asm/initialize_mmu.h 	movi	a4, CONFIG_MEMMAP_CACHEATTR
movi              219 arch/xtensa/include/asm/initialize_mmu.h 	movi	a8, 0x20000000