NB_PSTATE_CHANGE_WATERMARK_MASK  203 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c 				NB_PSTATE_CHANGE_WATERMARK_MASK, wm_select);
NB_PSTATE_CHANGE_WATERMARK_MASK  188 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h 	SFB(blk, DPG_WATERMARK_MASK_CONTROL, NB_PSTATE_CHANGE_WATERMARK_MASK, mask_sh),\
NB_PSTATE_CHANGE_WATERMARK_MASK  291 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h 	type NB_PSTATE_CHANGE_WATERMARK_MASK; \
NB_PSTATE_CHANGE_WATERMARK_MASK  834 drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c 		NB_PSTATE_CHANGE_WATERMARK_MASK);
NB_PSTATE_CHANGE_WATERMARK_MASK  871 drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c 		NB_PSTATE_CHANGE_WATERMARK_MASK);
NB_PSTATE_CHANGE_WATERMARK_MASK  144 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h 	SF(MCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL, NB_PSTATE_CHANGE_WATERMARK_MASK, mask_sh),\
NB_PSTATE_CHANGE_WATERMARK_MASK  209 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h 	type NB_PSTATE_CHANGE_WATERMARK_MASK;\
NB_PSTATE_CHANGE_WATERMARK_MASK  179 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.c 	REG_UPDATE(MCIF_WB_NB_PSTATE_CONTROL, NB_PSTATE_CHANGE_WATERMARK_MASK, 0x0);
NB_PSTATE_CHANGE_WATERMARK_MASK  183 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.c 	REG_UPDATE(MCIF_WB_NB_PSTATE_CONTROL, NB_PSTATE_CHANGE_WATERMARK_MASK, 0x1);
NB_PSTATE_CHANGE_WATERMARK_MASK  187 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.c 	REG_UPDATE(MCIF_WB_NB_PSTATE_CONTROL, NB_PSTATE_CHANGE_WATERMARK_MASK, 0x2);
NB_PSTATE_CHANGE_WATERMARK_MASK  191 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.c 	REG_UPDATE(MCIF_WB_NB_PSTATE_CONTROL, NB_PSTATE_CHANGE_WATERMARK_MASK, 0x3);
NB_PSTATE_CHANGE_WATERMARK_MASK  248 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h 	SF(MCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL, NB_PSTATE_CHANGE_WATERMARK_MASK, mask_sh),\
NB_PSTATE_CHANGE_WATERMARK_MASK  410 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h 	type NB_PSTATE_CHANGE_WATERMARK_MASK;\