NBIO 56 drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c return RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, NBIO 66 drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c reg = RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, NBIO 138 drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c reg = RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, NBIO 142 drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c WREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW0), NBIO 144 drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c WREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW1), NBIO 146 drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c WREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW2), NBIO 148 drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c WREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW3), NBIO 187 drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c SOC15_REG_OFFSET(NBIO, 0, NBIO 256 drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, NBIO 303 drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c u32 tmp = RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_INT_CNTL)); NBIO 307 drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c WREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_INT_CNTL), tmp); NBIO 356 drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c u32 tmp = RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_INT_CNTL)); NBIO 360 drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c WREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_INT_CNTL), tmp); NBIO 63 drivers/gpu/drm/amd/amdgpu/mxgpu_ai.h #define AI_MAIBOX_CONTROL_TRN_OFFSET_BYTE SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_CONTROL) * 4 NBIO 64 drivers/gpu/drm/amd/amdgpu/mxgpu_ai.h #define AI_MAIBOX_CONTROL_RCV_OFFSET_BYTE SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_CONTROL) * 4 + 1 NBIO 37 drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c u32 tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0); NBIO 48 drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c WREG32_SOC15(NBIO, 0, mmBIF_FB_EN, NBIO 52 drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c WREG32_SOC15(NBIO, 0, mmBIF_FB_EN, 0); NBIO 59 drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c WREG32_SOC15_NO_KIQ(NBIO, 0, mmBIF_BX_PF_HDP_MEM_COHERENCY_FLUSH_CNTL, 0); NBIO 62 drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c NBIO, 0, mmBIF_BX_PF_HDP_MEM_COHERENCY_FLUSH_CNTL), 0); NBIO 67 drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c return RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_RCC_CONFIG_MEMSIZE); NBIO 74 drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c u32 reg = instance == 0 ? SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA0_DOORBELL_RANGE) : NBIO 75 drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA1_DOORBELL_RANGE); NBIO 97 drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c u32 reg = SOC15_REG_OFFSET(NBIO, 0, mmBIF_MMSCH0_DOORBELL_RANGE); NBIO 117 drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c WREG32_FIELD15(NBIO, 0, RCC_DEV0_EPF0_RCC_DOORBELL_APER_EN, BIF_DOORBELL_APER_EN, NBIO 134 drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c WREG32_SOC15(NBIO, 0, mmBIF_BX_PF_DOORBELL_SELFRING_GPA_APER_BASE_LOW, NBIO 136 drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c WREG32_SOC15(NBIO, 0, mmBIF_BX_PF_DOORBELL_SELFRING_GPA_APER_BASE_HIGH, NBIO 140 drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c WREG32_SOC15(NBIO, 0, mmBIF_BX_PF_DOORBELL_SELFRING_GPA_APER_CNTL, NBIO 148 drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c u32 ih_doorbell_range = RREG32_SOC15(NBIO, 0, mmBIF_IH_DOORBELL_RANGE); NBIO 162 drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c WREG32_SOC15(NBIO, 0, mmBIF_IH_DOORBELL_RANGE, ih_doorbell_range); NBIO 170 drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c WREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL2, adev->dummy_page_addr >> 8); NBIO 172 drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c interrupt_cntl = RREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL); NBIO 184 drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c WREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL, interrupt_cntl); NBIO 251 drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c return SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF_GPU_HDP_FLUSH_REQ); NBIO 256 drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c return SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF_GPU_HDP_FLUSH_DONE); NBIO 261 drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_INDEX2); NBIO 266 drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_DATA2); NBIO 288 drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c reg = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_RCC_IOV_FUNC_IDENTIFIER); NBIO 35 drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c u32 tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0); NBIO 46 drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c WREG32_SOC15(NBIO, 0, mmBIF_FB_EN, NBIO 50 drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c WREG32_SOC15(NBIO, 0, mmBIF_FB_EN, 0); NBIO 57 drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c WREG32_SOC15_NO_KIQ(NBIO, 0, NBIO 62 drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c NBIO, 0, mmBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL), 0); NBIO 67 drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c return RREG32_SOC15(NBIO, 0, mmRCC_PF_0_0_RCC_CONFIG_MEMSIZE); NBIO 73 drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c u32 reg = instance == 0 ? SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA0_DOORBELL_RANGE) : NBIO 74 drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA1_DOORBELL_RANGE); NBIO 91 drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c WREG32_FIELD15(NBIO, 0, RCC_PF_0_0_RCC_DOORBELL_APER_EN, BIF_DOORBELL_APER_EN, enable ? 1 : 0); NBIO 104 drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c WREG32_SOC15(NBIO, 0, mmBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW, NBIO 106 drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c WREG32_SOC15(NBIO, 0, mmBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH, NBIO 110 drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c WREG32_SOC15(NBIO, 0, mmBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL, tmp); NBIO 117 drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c u32 ih_doorbell_range = RREG32_SOC15(NBIO, 0 , mmBIF_IH_DOORBELL_RANGE); NBIO 126 drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c WREG32_SOC15(NBIO, 0, mmBIF_IH_DOORBELL_RANGE, ih_doorbell_range); NBIO 134 drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c WREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL2, adev->dummy_page_addr >> 8); NBIO 135 drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c interrupt_cntl = RREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL); NBIO 142 drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c WREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL, interrupt_cntl); NBIO 211 drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c return SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_GPU_HDP_FLUSH_REQ); NBIO 216 drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c return SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_GPU_HDP_FLUSH_DONE); NBIO 221 drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_INDEX2); NBIO 226 drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_DATA2); NBIO 248 drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c reg = RREG32_SOC15(NBIO, 0, mmRCC_PF_0_0_RCC_IOV_FUNC_IDENTIFIER); NBIO 38 drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c WREG32_SOC15(NBIO, 0, mmREMAP_HDP_MEM_FLUSH_CNTL, NBIO 40 drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c WREG32_SOC15(NBIO, 0, mmREMAP_HDP_REG_FLUSH_CNTL, NBIO 46 drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c u32 tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0); NBIO 57 drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c WREG32_SOC15(NBIO, 0, mmBIF_FB_EN, NBIO 60 drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c WREG32_SOC15(NBIO, 0, mmBIF_FB_EN, 0); NBIO 74 drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c return RREG32_SOC15(NBIO, 0, mmRCC_CONFIG_MEMSIZE); NBIO 80 drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c u32 reg = instance == 0 ? SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA0_DOORBELL_RANGE) : NBIO 81 drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA1_DOORBELL_RANGE); NBIO 97 drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c u32 reg = SOC15_REG_OFFSET(NBIO, 0, mmBIF_MMSCH0_DOORBELL_RANGE); NBIO 117 drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c WREG32_FIELD15(NBIO, 0, RCC_DOORBELL_APER_EN, BIF_DOORBELL_APER_EN, enable ? 1 : 0); NBIO 129 drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c u32 ih_doorbell_range = RREG32_SOC15(NBIO, 0 , mmBIF_IH_DOORBELL_RANGE); NBIO 137 drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c WREG32_SOC15(NBIO, 0, mmBIF_IH_DOORBELL_RANGE, ih_doorbell_range); NBIO 144 drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c WREG32_SOC15(NBIO, 0, mmSYSHUB_INDEX, offset); NBIO 145 drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c data = RREG32_SOC15(NBIO, 0, mmSYSHUB_DATA); NBIO 153 drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c WREG32_SOC15(NBIO, 0, mmSYSHUB_INDEX, offset); NBIO 154 drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c WREG32_SOC15(NBIO, 0, mmSYSHUB_DATA, data); NBIO 237 drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c WREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL2, adev->dummy_page_addr >> 8); NBIO 238 drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c interrupt_cntl = RREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL); NBIO 245 drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c WREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL, interrupt_cntl); NBIO 250 drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c return SOC15_REG_OFFSET(NBIO, 0, mmGPU_HDP_FLUSH_REQ); NBIO 255 drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c return SOC15_REG_OFFSET(NBIO, 0, mmGPU_HDP_FLUSH_DONE); NBIO 260 drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_INDEX2); NBIO 265 drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_DATA2); NBIO 55 drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c WREG32_SOC15(NBIO, 0, mmREMAP_HDP_MEM_FLUSH_CNTL, NBIO 57 drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c WREG32_SOC15(NBIO, 0, mmREMAP_HDP_REG_FLUSH_CNTL, NBIO 63 drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c u32 tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0); NBIO 74 drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c WREG32_SOC15(NBIO, 0, mmBIF_FB_EN, NBIO 77 drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c WREG32_SOC15(NBIO, 0, mmBIF_FB_EN, 0); NBIO 91 drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c return RREG32_SOC15(NBIO, 0, mmRCC_CONFIG_MEMSIZE); NBIO 101 drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA0_DOORBELL_RANGE); NBIO 112 drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA0_DOORBELL_RANGE); NBIO 132 drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c reg = SOC15_REG_OFFSET(NBIO, 0, mmBIF_MMSCH1_DOORBELL_RANGE); NBIO 134 drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c reg = SOC15_REG_OFFSET(NBIO, 0, mmBIF_MMSCH0_DOORBELL_RANGE); NBIO 154 drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c WREG32_FIELD15(NBIO, 0, RCC_DOORBELL_APER_EN, BIF_DOORBELL_APER_EN, enable ? 1 : 0); NBIO 167 drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c WREG32_SOC15(NBIO, 0, mmDOORBELL_SELFRING_GPA_APER_BASE_LOW, NBIO 169 drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c WREG32_SOC15(NBIO, 0, mmDOORBELL_SELFRING_GPA_APER_BASE_HIGH, NBIO 173 drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c WREG32_SOC15(NBIO, 0, mmDOORBELL_SELFRING_GPA_APER_CNTL, tmp); NBIO 179 drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c u32 ih_doorbell_range = RREG32_SOC15(NBIO, 0 , mmBIF_IH_DOORBELL_RANGE); NBIO 187 drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c WREG32_SOC15(NBIO, 0, mmBIF_IH_DOORBELL_RANGE, ih_doorbell_range); NBIO 238 drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c WREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL2, adev->dummy_page_addr >> 8); NBIO 239 drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c interrupt_cntl = RREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL); NBIO 246 drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c WREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL, interrupt_cntl); NBIO 251 drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c return SOC15_REG_OFFSET(NBIO, 0, mmGPU_HDP_FLUSH_REQ); NBIO 256 drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c return SOC15_REG_OFFSET(NBIO, 0, mmGPU_HDP_FLUSH_DONE); NBIO 261 drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_INDEX2); NBIO 266 drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_DATA2); NBIO 294 drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c reg = RREG32_SOC15(NBIO, 0, mmRCC_IOV_FUNC_IDENTIFIER); NBIO 497 drivers/gpu/drm/amd/amdgpu/nv.c WREG32_SOC15_NO_KIQ(NBIO, 0, mmHDP_READ_CACHE_INVALIDATE, 1); NBIO 1661 drivers/gpu/drm/amd/powerplay/smu_v11_0.c val = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP0);