NBIF0_BASE         39 drivers/gpu/drm/amd/amdgpu/arct_reg_init.c 		adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIF0_BASE.instance[i]));
NBIF0_BASE         39 drivers/gpu/drm/amd/amdgpu/navi12_reg_init.c 		adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIF0_BASE.instance[i]));
NBIF0_BASE         39 drivers/gpu/drm/amd/amdgpu/navi14_reg_init.c 		adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIF0_BASE.instance[i]));
NBIF0_BASE        111 drivers/gpu/drm/amd/include/arct_ip_offset.h static const struct IP_BASE NBIF0_BASE            ={ { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0x00012D80, 0x0041B000 } },
NBIF0_BASE        130 drivers/gpu/drm/amd/include/navi12_ip_offset.h static const struct IP_BASE NBIF0_BASE ={ { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0x0241B000 } },
NBIF0_BASE        130 drivers/gpu/drm/amd/include/navi14_ip_offset.h static const struct IP_BASE NBIF0_BASE ={ { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0x0241B000 } },
NBIF0_BASE        165 drivers/gpu/drm/amd/include/renoir_ip_offset.h static const struct IP_BASE NBIF0_BASE ={ { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0x0241B000 } },