mode_reg 493 arch/arm/mach-pxa/hx4700.c .mode_reg = 0x00250000, mode_reg 400 arch/powerpc/platforms/powermac/low_i2c.c u8 mode_reg = host->speed; mode_reg 408 arch/powerpc/platforms/powermac/low_i2c.c mode_reg |= KW_I2C_MODE_STANDARD; mode_reg 413 arch/powerpc/platforms/powermac/low_i2c.c mode_reg |= KW_I2C_MODE_STANDARDSUB; mode_reg 418 arch/powerpc/platforms/powermac/low_i2c.c mode_reg |= KW_I2C_MODE_COMBINED; mode_reg 426 arch/powerpc/platforms/powermac/low_i2c.c kw_write_reg(reg_mode, mode_reg | (bus->channel << 4)); mode_reg 435 arch/powerpc/platforms/powermac/low_i2c.c if ((mode_reg & KW_I2C_MODE_MODE_MASK) == KW_I2C_MODE_STANDARDSUB mode_reg 436 arch/powerpc/platforms/powermac/low_i2c.c || (mode_reg & KW_I2C_MODE_MODE_MASK) == KW_I2C_MODE_COMBINED) mode_reg 105 drivers/atm/uPD98402.c unsigned char mode_reg; mode_reg 107 drivers/atm/uPD98402.c mode_reg = GET(MDR) & ~(uPD98402_MDR_TPLP | uPD98402_MDR_ALP | mode_reg 113 drivers/atm/uPD98402.c mode_reg |= uPD98402_MDR_TPLP; mode_reg 116 drivers/atm/uPD98402.c mode_reg |= uPD98402_MDR_ALP; mode_reg 125 drivers/atm/uPD98402.c mode_reg |= uPD98402_MDR_RPLP; mode_reg 130 drivers/atm/uPD98402.c PUT(mode_reg,MDR); mode_reg 64 drivers/clk/qcom/a53-pll.c pll->mode_reg = 0x00; mode_reg 63 drivers/clk/qcom/clk-hfpll.c regmap_update_bits(regmap, hd->mode_reg, PLL_BYPASSNL, PLL_BYPASSNL); mode_reg 72 drivers/clk/qcom/clk-hfpll.c regmap_update_bits(regmap, hd->mode_reg, PLL_RESET_N, PLL_RESET_N); mode_reg 84 drivers/clk/qcom/clk-hfpll.c regmap_update_bits(regmap, hd->mode_reg, PLL_OUTCTRL, PLL_OUTCTRL); mode_reg 97 drivers/clk/qcom/clk-hfpll.c regmap_read(regmap, hd->mode_reg, &mode); mode_reg 114 drivers/clk/qcom/clk-hfpll.c regmap_update_bits(regmap, hd->mode_reg, mode_reg 206 drivers/clk/qcom/clk-hfpll.c regmap_read(regmap, hd->mode_reg, &mode); mode_reg 230 drivers/clk/qcom/clk-hfpll.c regmap_read(regmap, hd->mode_reg, &mode); mode_reg 11 drivers/clk/qcom/clk-hfpll.h u32 mode_reg; mode_reg 31 drivers/clk/qcom/clk-pll.c ret = regmap_read(pll->clkr.regmap, pll->mode_reg, &val); mode_reg 40 drivers/clk/qcom/clk-pll.c ret = regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_BYPASSNL, mode_reg 52 drivers/clk/qcom/clk-pll.c ret = regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_RESET_N, mode_reg 61 drivers/clk/qcom/clk-pll.c return regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_OUTCTRL, mode_reg 71 drivers/clk/qcom/clk-pll.c regmap_read(pll->clkr.regmap, pll->mode_reg, &val); mode_reg 76 drivers/clk/qcom/clk-pll.c regmap_update_bits(pll->clkr.regmap, pll->mode_reg, mask, 0); mode_reg 153 drivers/clk/qcom/clk-pll.c regmap_read(pll->clkr.regmap, pll->mode_reg, &mode); mode_reg 250 drivers/clk/qcom/clk-pll.c qcom_pll_set_fsm_mode(regmap, pll->mode_reg, 1, 8); mode_reg 259 drivers/clk/qcom/clk-pll.c qcom_pll_set_fsm_mode(regmap, pll->mode_reg, 1, 0); mode_reg 269 drivers/clk/qcom/clk-pll.c ret = regmap_read(pll->clkr.regmap, pll->mode_reg, &mode); mode_reg 274 drivers/clk/qcom/clk-pll.c ret = regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_BYPASSNL, mode_reg 286 drivers/clk/qcom/clk-pll.c ret = regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_RESET_N, mode_reg 296 drivers/clk/qcom/clk-pll.c return regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_OUTCTRL, mode_reg 313 drivers/clk/qcom/clk-pll.c regmap_read(pll->clkr.regmap, pll->mode_reg, &mode); mode_reg 44 drivers/clk/qcom/clk-pll.h u32 mode_reg; mode_reg 106 drivers/clk/qcom/gcc-apq8084.c .mode_reg = 0x0000, mode_reg 169 drivers/clk/qcom/gcc-apq8084.c .mode_reg = 0x0040, mode_reg 196 drivers/clk/qcom/gcc-apq8084.c .mode_reg = 0x1dc0, mode_reg 33 drivers/clk/qcom/gcc-ipq806x.c .mode_reg = 0x30c0, mode_reg 60 drivers/clk/qcom/gcc-ipq806x.c .mode_reg = 0x3160, mode_reg 87 drivers/clk/qcom/gcc-ipq806x.c .mode_reg = 0x3140, mode_reg 110 drivers/clk/qcom/gcc-ipq806x.c .mode_reg = 0x3200, mode_reg 136 drivers/clk/qcom/gcc-ipq806x.c .mode_reg = 0x3240, mode_reg 162 drivers/clk/qcom/gcc-ipq806x.c .mode_reg = 0x3300, mode_reg 192 drivers/clk/qcom/gcc-ipq806x.c .mode_reg = 0x31c0, mode_reg 233 drivers/clk/qcom/gcc-ipq806x.c .mode_reg = 0x31a0, mode_reg 45 drivers/clk/qcom/gcc-mdm9615.c .mode_reg = 0x30c0, mode_reg 83 drivers/clk/qcom/gcc-mdm9615.c .mode_reg = 0x3140, mode_reg 110 drivers/clk/qcom/gcc-mdm9615.c .mode_reg = 0x31c0, mode_reg 32 drivers/clk/qcom/gcc-msm8660.c .mode_reg = 0x3140, mode_reg 264 drivers/clk/qcom/gcc-msm8916.c .mode_reg = 0x21000, mode_reg 291 drivers/clk/qcom/gcc-msm8916.c .mode_reg = 0x20000, mode_reg 318 drivers/clk/qcom/gcc-msm8916.c .mode_reg = 0x4a000, mode_reg 345 drivers/clk/qcom/gcc-msm8916.c .mode_reg = 0x23000, mode_reg 33 drivers/clk/qcom/gcc-msm8960.c .mode_reg = 0x3160, mode_reg 60 drivers/clk/qcom/gcc-msm8960.c .mode_reg = 0x3140, mode_reg 83 drivers/clk/qcom/gcc-msm8960.c .mode_reg = 0x3200, mode_reg 109 drivers/clk/qcom/gcc-msm8960.c .mode_reg = 0x3240, mode_reg 123 drivers/clk/qcom/gcc-msm8960.c .mode_reg = 0x3300, mode_reg 149 drivers/clk/qcom/gcc-msm8960.c .mode_reg = 0x3280, mode_reg 175 drivers/clk/qcom/gcc-msm8960.c .mode_reg = 0x32c0, mode_reg 201 drivers/clk/qcom/gcc-msm8960.c .mode_reg = 0x3300, mode_reg 215 drivers/clk/qcom/gcc-msm8960.c .mode_reg = 0x3400, mode_reg 245 drivers/clk/qcom/gcc-msm8960.c .mode_reg = 0x31c0, mode_reg 62 drivers/clk/qcom/gcc-msm8974.c .mode_reg = 0x0000, mode_reg 125 drivers/clk/qcom/gcc-msm8974.c .mode_reg = 0x0040, mode_reg 152 drivers/clk/qcom/gcc-msm8974.c .mode_reg = 0x1dc0, mode_reg 404 drivers/clk/qcom/gcc-qcs404.c .mode_reg = 0x37000, mode_reg 17 drivers/clk/qcom/hfpll.c .mode_reg = 0x00, mode_reg 31 drivers/clk/qcom/lcc-ipq806x.c .mode_reg = 0x0, mode_reg 33 drivers/clk/qcom/lcc-mdm9615.c .mode_reg = 0x0, mode_reg 31 drivers/clk/qcom/lcc-msm8960.c .mode_reg = 0x0, mode_reg 219 drivers/clk/qcom/mmcc-apq8084.c .mode_reg = 0x0000, mode_reg 246 drivers/clk/qcom/mmcc-apq8084.c .mode_reg = 0x0040, mode_reg 273 drivers/clk/qcom/mmcc-apq8084.c .mode_reg = 0x4100, mode_reg 288 drivers/clk/qcom/mmcc-apq8084.c .mode_reg = 0x0080, mode_reg 304 drivers/clk/qcom/mmcc-apq8084.c .mode_reg = 0x0080, mode_reg 113 drivers/clk/qcom/mmcc-msm8960.c .mode_reg = 0x31c, mode_reg 129 drivers/clk/qcom/mmcc-msm8960.c .mode_reg = 0x338, mode_reg 184 drivers/clk/qcom/mmcc-msm8974.c .mode_reg = 0x0000, mode_reg 211 drivers/clk/qcom/mmcc-msm8974.c .mode_reg = 0x0040, mode_reg 238 drivers/clk/qcom/mmcc-msm8974.c .mode_reg = 0x4100, mode_reg 253 drivers/clk/qcom/mmcc-msm8974.c .mode_reg = 0x0080, mode_reg 202 drivers/clk/spear/clk-vco-pll.c mode = (readl_relaxed(vco->mode_reg) >> PLL_MODE_SHIFT) & PLL_MODE_MASK; mode_reg 244 drivers/clk/spear/clk-vco-pll.c val = readl_relaxed(vco->mode_reg); mode_reg 247 drivers/clk/spear/clk-vco-pll.c writel_relaxed(val, vco->mode_reg); mode_reg 277 drivers/clk/spear/clk-vco-pll.c unsigned long flags, void __iomem *mode_reg, void __iomem mode_reg 288 drivers/clk/spear/clk-vco-pll.c if (!vco_name || !pll_name || !parent_name || !mode_reg || !cfg_reg || mode_reg 303 drivers/clk/spear/clk-vco-pll.c vco->mode_reg = mode_reg; mode_reg 315 drivers/clk/spear/clk-vco-pll.c parent_name, 0, mode_reg, PLL_ENABLE, 0, lock); mode_reg 95 drivers/clk/spear/clk.h void __iomem *mode_reg; mode_reg 125 drivers/clk/spear/clk.h unsigned long flags, void __iomem *mode_reg, void __iomem mode_reg 62 drivers/gpu/drm/nouveau/dispnv04/crtc.c struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index]; mode_reg 77 drivers/gpu/drm/nouveau/dispnv04/crtc.c struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index]; mode_reg 119 drivers/gpu/drm/nouveau/dispnv04/crtc.c struct nv04_mode_state *state = &nv04_display(dev)->mode_reg; mode_reg 236 drivers/gpu/drm/nouveau/dispnv04/crtc.c struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index]; mode_reg 461 drivers/gpu/drm/nouveau/dispnv04/crtc.c struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index]; mode_reg 653 drivers/gpu/drm/nouveau/dispnv04/crtc.c NVWriteRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK, nv04_display(dev)->mode_reg.sel_clk); mode_reg 663 drivers/gpu/drm/nouveau/dispnv04/crtc.c struct nv04_mode_state *state = &nv04_display(dev)->mode_reg; mode_reg 725 drivers/gpu/drm/nouveau/dispnv04/crtc.c nouveau_hw_load_state(dev, nv_crtc->index, &nv04_display(dev)->mode_reg); mode_reg 770 drivers/gpu/drm/nouveau/dispnv04/crtc.c rgbs = (struct rgb *)nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index].DAC; mode_reg 781 drivers/gpu/drm/nouveau/dispnv04/crtc.c nouveau_hw_load_state_palette(dev, nv_crtc->index, &nv04_display(dev)->mode_reg); mode_reg 824 drivers/gpu/drm/nouveau/dispnv04/crtc.c struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index]; mode_reg 42 drivers/gpu/drm/nouveau/dispnv04/cursor.c struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index]; mode_reg 95 drivers/gpu/drm/nouveau/dispnv04/dfp.c struct nv04_crtc_reg *crtcstate = nv04_display(dev)->mode_reg.crtc_reg; mode_reg 122 drivers/gpu/drm/nouveau/dispnv04/dfp.c fpc = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index].fp_control; mode_reg 137 drivers/gpu/drm/nouveau/dispnv04/dfp.c fpc = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index].fp_control; mode_reg 206 drivers/gpu/drm/nouveau/dispnv04/dfp.c struct nv04_mode_state *state = &nv04_display(dev)->mode_reg; mode_reg 250 drivers/gpu/drm/nouveau/dispnv04/dfp.c struct nv04_crtc_reg *crtcstate = nv04_display(dev)->mode_reg.crtc_reg; mode_reg 287 drivers/gpu/drm/nouveau/dispnv04/dfp.c struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index]; mode_reg 463 drivers/gpu/drm/nouveau/dispnv04/dfp.c nv04_display(dev)->mode_reg.crtc_reg[head].fp_control = mode_reg 554 drivers/gpu/drm/nouveau/dispnv04/dfp.c nv04_display(dev)->mode_reg.sel_clk = NVReadRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK); mode_reg 555 drivers/gpu/drm/nouveau/dispnv04/dfp.c nv04_display(dev)->mode_reg.sel_clk &= ~0xf0; mode_reg 557 drivers/gpu/drm/nouveau/dispnv04/dfp.c NVWriteRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK, nv04_display(dev)->mode_reg.sel_clk); mode_reg 80 drivers/gpu/drm/nouveau/dispnv04/disp.h struct nv04_mode_state mode_reg; mode_reg 376 drivers/gpu/drm/nouveau/dispnv04/hw.h &nv04_display(dev)->mode_reg.crtc_reg[head].CRTC[NV_CIO_CRE_HCUR_ADDR1_INDEX]; mode_reg 547 drivers/gpu/drm/nouveau/dispnv04/tvmodesnv17.c struct nv04_crtc_reg *regs = &nv04_display(dev)->mode_reg.crtc_reg[head]; mode_reg 79 drivers/gpu/drm/nouveau/dispnv04/tvnv04.c struct nv04_mode_state *state = &nv04_display(dev)->mode_reg; mode_reg 107 drivers/gpu/drm/nouveau/dispnv04/tvnv04.c struct nv04_crtc_reg *state = &nv04_display(dev)->mode_reg.crtc_reg[head]; mode_reg 146 drivers/gpu/drm/nouveau/dispnv04/tvnv04.c struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index]; mode_reg 403 drivers/gpu/drm/nouveau/dispnv04/tvnv17.c uint8_t *cr_lcd = &nv04_display(dev)->mode_reg.crtc_reg[head].CRTC[ mode_reg 464 drivers/gpu/drm/nouveau/dispnv04/tvnv17.c struct nv04_crtc_reg *regs = &nv04_display(dev)->mode_reg.crtc_reg[head]; mode_reg 74 drivers/media/i2c/lm3646.c u8 mode_reg; mode_reg 87 drivers/media/i2c/lm3646.c REG_ENABLE, flash->mode_reg | MODE_SHDN); mode_reg 90 drivers/media/i2c/lm3646.c REG_ENABLE, flash->mode_reg | MODE_TORCH); mode_reg 93 drivers/media/i2c/lm3646.c REG_ENABLE, flash->mode_reg | MODE_FLASH); mode_reg 303 drivers/media/i2c/lm3646.c flash->mode_reg = reg_val & 0xfc; mode_reg 77 drivers/media/i2c/msp3400-kthreads.c int mode_reg; mode_reg 224 drivers/media/i2c/msp3400-kthreads.c msp_write_dem(client, 0x0083, data->mode_reg); mode_reg 441 drivers/mfd/menelaus.c u8 mode_reg; mode_reg 470 drivers/mfd/menelaus.c ret = menelaus_write_reg(vtg->mode_reg, mode); mode_reg 564 drivers/mfd/menelaus.c .mode_reg = MENELAUS_LDO_CTRL3, mode_reg 593 drivers/mfd/menelaus.c .mode_reg = MENELAUS_LDO_CTRL4, mode_reg 633 drivers/mfd/menelaus.c .mode_reg = MENELAUS_DCDC_CTRL2, mode_reg 641 drivers/mfd/menelaus.c .mode_reg = MENELAUS_DCDC_CTRL3, mode_reg 678 drivers/mfd/menelaus.c .mode_reg = MENELAUS_LDO_CTRL7, mode_reg 708 drivers/mfd/menelaus.c .mode_reg = MENELAUS_LDO_CTRL6, mode_reg 337 drivers/mmc/host/atmel-mci.c u32 mode_reg; mode_reg 864 drivers/mmc/host/atmel-mci.c atmci_writel(host, ATMCI_MR, host->mode_reg | ATMCI_MR_PDCFBYTE); mode_reg 1048 drivers/mmc/host/atmel-mci.c atmci_writel(host, ATMCI_MR, host->mode_reg | ATMCI_MR_PDCMODE); mode_reg 1250 drivers/mmc/host/atmel-mci.c atmci_writel(host, ATMCI_MR, host->mode_reg); mode_reg 1396 drivers/mmc/host/atmel-mci.c if (!host->mode_reg) { mode_reg 1428 drivers/mmc/host/atmel-mci.c host->mode_reg = ATMCI_MR_CLKDIV(clkdiv >> 1) mode_reg 1438 drivers/mmc/host/atmel-mci.c host->mode_reg = ATMCI_MR_CLKDIV(clkdiv); mode_reg 1447 drivers/mmc/host/atmel-mci.c host->mode_reg |= (ATMCI_MR_WRPROOF | ATMCI_MR_RDPROOF); mode_reg 1458 drivers/mmc/host/atmel-mci.c atmci_writel(host, ATMCI_MR, host->mode_reg); mode_reg 1479 drivers/mmc/host/atmel-mci.c if (host->mode_reg) { mode_reg 1482 drivers/mmc/host/atmel-mci.c host->mode_reg = 0; mode_reg 1566 drivers/mmc/host/atmel-mci.c atmci_writel(host, ATMCI_MR, host->mode_reg); mode_reg 1667 drivers/mmc/host/atmel-mci.c atmci_writel(host, ATMCI_MR, host->mode_reg); mode_reg 175 drivers/net/ethernet/dnet.c u32 mode_reg, ctl_reg; mode_reg 181 drivers/net/ethernet/dnet.c mode_reg = dnet_readw_mac(bp, DNET_INTERNAL_MODE_REG); mode_reg 201 drivers/net/ethernet/dnet.c mode_reg |= DNET_INTERNAL_MODE_GBITEN; mode_reg 205 drivers/net/ethernet/dnet.c mode_reg &= ~DNET_INTERNAL_MODE_GBITEN; mode_reg 220 drivers/net/ethernet/dnet.c mode_reg |= mode_reg 223 drivers/net/ethernet/dnet.c mode_reg &= mode_reg 236 drivers/net/ethernet/dnet.c dnet_writew_mac(bp, DNET_INTERNAL_MODE_REG, mode_reg); mode_reg 99 drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c u32 mode_reg; /* MAC glue-logic mode register */ mode_reg 177 drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c u32 reg = dwmac->mode_reg; mode_reg 225 drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c u32 reg = dwmac->mode_reg; mode_reg 287 drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c err = of_property_read_u32_index(np, "st,syscon", 1, &dwmac->mode_reg); mode_reg 75 drivers/regulator/ab8500.c u8 mode_reg; mode_reg 327 drivers/regulator/ab8500.c reg = info->mode_reg; mode_reg 425 drivers/regulator/ab8500.c info->mode_bank, info->mode_reg, &val); mode_reg 990 drivers/regulator/ab8500.c .mode_reg = 0x54, mode_reg 1011 drivers/regulator/ab8500.c .mode_reg = 0x54, mode_reg 104 drivers/regulator/fan53555.c unsigned int mode_reg; mode_reg 153 drivers/regulator/fan53555.c regmap_update_bits(rdev->regmap, di->mode_reg, mode_reg 171 drivers/regulator/fan53555.c ret = regmap_read(rdev->regmap, di->mode_reg, &val); mode_reg 347 drivers/regulator/fan53555.c di->mode_reg = FAN53555_CONTROL; mode_reg 360 drivers/regulator/fan53555.c di->mode_reg = di->vol_reg; mode_reg 38 drivers/regulator/pv88080-regulator.c unsigned int mode_reg; mode_reg 215 drivers/regulator/pv88080-regulator.c ret = regmap_read(rdev->regmap, info->mode_reg, &data); mode_reg 256 drivers/regulator/pv88080-regulator.c return regmap_update_bits(rdev->regmap, info->mode_reg, mode_reg 483 drivers/regulator/pv88080-regulator.c pv88080_regulator_info[i].mode_reg mode_reg 22 drivers/regulator/sy8824x.c unsigned int mode_reg; mode_reg 44 drivers/regulator/sy8824x.c regmap_update_bits(rdev->regmap, cfg->mode_reg, mode_reg 48 drivers/regulator/sy8824x.c regmap_update_bits(rdev->regmap, cfg->mode_reg, mode_reg 64 drivers/regulator/sy8824x.c ret = regmap_read(rdev->regmap, cfg->mode_reg, &val); mode_reg 159 drivers/regulator/sy8824x.c .mode_reg = 0x00, mode_reg 168 drivers/regulator/sy8824x.c .mode_reg = 0x00, mode_reg 177 drivers/regulator/sy8824x.c .mode_reg = 0x01, mode_reg 186 drivers/regulator/sy8824x.c .mode_reg = 0x01, mode_reg 1438 drivers/scsi/nsp32.c unsigned char mode_reg; mode_reg 1455 drivers/scsi/nsp32.c mode_reg = nsp32_index_read1(base, CHIP_MODE); mode_reg 1459 drivers/scsi/nsp32.c seq_printf(m, "Power Management: %s\n", (mode_reg & OPTF) ? "yes" : "no"); mode_reg 1461 drivers/scsi/nsp32.c seq_printf(m, "OEM: %ld, %s\n", (mode_reg & (OEM0|OEM1)), nsp32_model[model]); mode_reg 690 drivers/tty/serial/xilinx_uartps.c unsigned int ctrl_reg, mode_reg, val; mode_reg 765 drivers/tty/serial/xilinx_uartps.c mode_reg = readl(port->membase + CDNS_UART_MR); mode_reg 805 drivers/tty/serial/xilinx_uartps.c cval |= mode_reg & 1; mode_reg 1021 drivers/tty/serial/xilinx_uartps.c u32 mode_reg; mode_reg 1028 drivers/tty/serial/xilinx_uartps.c mode_reg = readl(port->membase + CDNS_UART_MR); mode_reg 1032 drivers/tty/serial/xilinx_uartps.c mode_reg &= ~CDNS_UART_MR_CHMODE_MASK; mode_reg 1037 drivers/tty/serial/xilinx_uartps.c mode_reg |= CDNS_UART_MR_CHMODE_L_LOOP; mode_reg 1039 drivers/tty/serial/xilinx_uartps.c mode_reg |= CDNS_UART_MR_CHMODE_NORM; mode_reg 1042 drivers/tty/serial/xilinx_uartps.c writel(mode_reg, port->membase + CDNS_UART_MR); mode_reg 1406 drivers/video/fbdev/w100fb.c writel(bm_mem->mode_reg, remapped_regs + mmBM_MEM_MODE_REG); mode_reg 61 include/video/w100fb.h unsigned long mode_reg; mode_reg 109 sound/soc/codecs/wm8998.c unsigned int mode_reg, mode_index; mode_reg 118 sound/soc/codecs/wm8998.c mode_reg = ARIZONA_IN2L_CONTROL; mode_reg 122 sound/soc/codecs/wm8998.c mode_reg = ARIZONA_IN1L_CONTROL; mode_reg 137 sound/soc/codecs/wm8998.c snd_soc_component_update_bits(component, mode_reg, mode_reg 180 sound/soc/sh/rcar/ssiu.c enum rsnd_reg adinr_reg, mode_reg, dalign_reg; mode_reg 184 sound/soc/sh/rcar/ssiu.c mode_reg = SSI9_BUSIF_MODE(busif); mode_reg 188 sound/soc/sh/rcar/ssiu.c mode_reg = SSI_BUSIF_MODE(busif); mode_reg 197 sound/soc/sh/rcar/ssiu.c rsnd_mod_write(mod, mode_reg,