mode_offset        18 arch/arm/mach-davinci/mux.h #define MUX_CFG(soc, desc, muxreg, mode_offset, mode_mask, mux_mode, dbg)\
mode_offset        24 arch/arm/mach-davinci/mux.h 			.mask_offset = mode_offset,			\
mode_offset        29 arch/arm/mach-davinci/mux.h #define INT_CFG(soc, desc, mode_offset, mode_mask, mux_mode, dbg)	\
mode_offset        35 arch/arm/mach-davinci/mux.h 			.mask_offset = mode_offset,			\
mode_offset        40 arch/arm/mach-davinci/mux.h #define EVT_CFG(soc, desc, mode_offset, mode_mask, mux_mode, dbg)	\
mode_offset        46 arch/arm/mach-davinci/mux.h 			.mask_offset = mode_offset,			\
mode_offset        27 arch/arm/mach-omap1/include/mach/mux.h #define MUX_REG(reg, mode_offset, mode) .mux_reg_name = "FUNC_MUX_CTRL_"#reg, \
mode_offset        29 arch/arm/mach-omap1/include/mach/mux.h 					.mask_offset = mode_offset, \
mode_offset        41 arch/arm/mach-omap1/include/mach/mux.h #define MUX_REG_7XX(reg, mode_offset, mode) .mux_reg_name = "OMAP7XX_IO_CONF_"#reg, \
mode_offset        43 arch/arm/mach-omap1/include/mach/mux.h 					.mask_offset = mode_offset, \
mode_offset        53 arch/arm/mach-omap1/include/mach/mux.h #define MUX_REG(reg, mode_offset, mode) .mux_reg = FUNC_MUX_CTRL_##reg, \
mode_offset        54 arch/arm/mach-omap1/include/mach/mux.h 					.mask_offset = mode_offset, \
mode_offset        64 arch/arm/mach-omap1/include/mach/mux.h #define MUX_REG_7XX(reg, mode_offset, mode) \
mode_offset        66 arch/arm/mach-omap1/include/mach/mux.h 					.mask_offset = mode_offset, \
mode_offset        75 arch/arm/mach-omap1/include/mach/mux.h #define MUX_CFG(desc, mux_reg, mode_offset, mode,	\
mode_offset        81 arch/arm/mach-omap1/include/mach/mux.h 	MUX_REG(mux_reg, mode_offset, mode)		\
mode_offset        94 arch/arm/mach-omap1/include/mach/mux.h #define MUX_CFG_7XX(desc, mux_reg, mode_offset, mode,	\
mode_offset        99 arch/arm/mach-omap1/include/mach/mux.h 	MUX_REG_7XX(mux_reg, mode_offset, mode)		\
mode_offset      1673 drivers/block/pktcdvd.c 	pd->mode_offset = (buffer[6] << 8) | (buffer[7] & 0xff);
mode_offset      1691 drivers/block/pktcdvd.c 	wp = (write_param_page *) &buffer[sizeof(struct mode_page_header) + pd->mode_offset];
mode_offset      1925 drivers/block/pktcdvd.c 	cgc.buflen = pd->mode_offset + 12;
mode_offset      1936 drivers/block/pktcdvd.c 	buf[pd->mode_offset + 10] |= (!!set << 2);
mode_offset      1970 drivers/block/pktcdvd.c 	cap_buf = &buf[sizeof(struct mode_page_header) + pd->mode_offset];
mode_offset      1976 drivers/block/pktcdvd.c 		cgc.buflen = pd->mode_offset + cap_buf[1] + 2 +
mode_offset      2547 drivers/block/pktcdvd.c 	seq_printf(m, "\tmode page offset:\t%u\n", pd->mode_offset);
mode_offset       835 drivers/clk/rockchip/clk-pll.c 		int lock_shift, int mode_offset, int mode_shift,
mode_offset       862 drivers/clk/rockchip/clk-pll.c 	pll_mux->reg = ctx->reg_base + mode_offset;
mode_offset       424 drivers/clk/rockchip/clk.c 				list->lock_shift, list->mode_offset,
mode_offset       285 drivers/clk/rockchip/clk.h 	int			mode_offset;
mode_offset       305 drivers/clk/rockchip/clk.h 		.mode_offset	= _mode,				\
mode_offset       316 drivers/clk/rockchip/clk.h 		int lock_shift, int mode_offset, int mode_shift,
mode_offset        14 drivers/media/cec/cec-pin-error-inj.c 	unsigned int mode_offset;
mode_offset       195 drivers/media/cec/cec-pin-error-inj.c 		unsigned int mode_offset;
mode_offset       203 drivers/media/cec/cec-pin-error-inj.c 		mode_offset = cec_error_inj_cmds[i].mode_offset;
mode_offset       204 drivers/media/cec/cec-pin-error-inj.c 		mode_mask = CEC_ERROR_INJ_MODE_MASK << mode_offset;
mode_offset       207 drivers/media/cec/cec-pin-error-inj.c 		if (mode_offset == CEC_ERROR_INJ_RX_ARB_LOST_OFFSET) {
mode_offset       213 drivers/media/cec/cec-pin-error-inj.c 		} else if (mode_offset == CEC_ERROR_INJ_TX_ADD_BYTES_OFFSET) {
mode_offset       225 drivers/media/cec/cec-pin-error-inj.c 			if ((mode_offset == CEC_ERROR_INJ_TX_SHORT_BIT_OFFSET ||
mode_offset       226 drivers/media/cec/cec-pin-error-inj.c 			     mode_offset == CEC_ERROR_INJ_TX_LONG_BIT_OFFSET ||
mode_offset       227 drivers/media/cec/cec-pin-error-inj.c 			     mode_offset == CEC_ERROR_INJ_TX_CUSTOM_BIT_OFFSET) &&
mode_offset       232 drivers/media/cec/cec-pin-error-inj.c 		*error |= (u64)mode << mode_offset;
mode_offset       317 drivers/media/cec/cec-pin-error-inj.c 			unsigned int mode_offset;
mode_offset       320 drivers/media/cec/cec-pin-error-inj.c 			mode_offset = cec_error_inj_cmds[j].mode_offset;
mode_offset       322 drivers/media/cec/cec-pin-error-inj.c 			mode = (e >> mode_offset) & CEC_ERROR_INJ_MODE_MASK;
mode_offset       156 drivers/media/cec/cec-pin.c static bool rx_error_inj(struct cec_pin *pin, unsigned int mode_offset,
mode_offset       162 drivers/media/cec/cec-pin.c 	unsigned int mode = (e >> mode_offset) & CEC_ERROR_INJ_MODE_MASK;
mode_offset       176 drivers/media/cec/cec-pin.c 			~(CEC_ERROR_INJ_MODE_MASK << mode_offset);
mode_offset       218 drivers/media/cec/cec-pin.c static bool tx_error_inj(struct cec_pin *pin, unsigned int mode_offset,
mode_offset       224 drivers/media/cec/cec-pin.c 	unsigned int mode = (e >> mode_offset) & CEC_ERROR_INJ_MODE_MASK;
mode_offset       238 drivers/media/cec/cec-pin.c 			~(CEC_ERROR_INJ_MODE_MASK << mode_offset);
mode_offset       470 drivers/net/wireless/ath/ath5k/eeprom.c 	u32 mode_offset[3];
mode_offset       478 drivers/net/wireless/ath/ath5k/eeprom.c 	mode_offset[AR5K_EEPROM_MODE_11A] = AR5K_EEPROM_MODES_11A(ah->ah_ee_version);
mode_offset       479 drivers/net/wireless/ath/ath5k/eeprom.c 	mode_offset[AR5K_EEPROM_MODE_11B] = AR5K_EEPROM_MODES_11B(ah->ah_ee_version);
mode_offset       480 drivers/net/wireless/ath/ath5k/eeprom.c 	mode_offset[AR5K_EEPROM_MODE_11G] = AR5K_EEPROM_MODES_11G(ah->ah_ee_version);
mode_offset       486 drivers/net/wireless/ath/ath5k/eeprom.c 		offset = mode_offset[mode];
mode_offset       174 include/linux/pktcdvd.h 	__u8			mode_offset;	/* 0 / 8 */