mode_cmd 527 drivers/gpu/drm/amd/amdgpu/amdgpu_display.c const struct drm_mode_fb_cmd2 *mode_cmd, mode_cmd 532 drivers/gpu/drm/amd/amdgpu/amdgpu_display.c drm_helper_mode_fill_fb_struct(dev, &rfb->base, mode_cmd); mode_cmd 544 drivers/gpu/drm/amd/amdgpu/amdgpu_display.c const struct drm_mode_fb_cmd2 *mode_cmd) mode_cmd 550 drivers/gpu/drm/amd/amdgpu/amdgpu_display.c obj = drm_gem_object_lookup(file_priv, mode_cmd->handles[0]); mode_cmd 553 drivers/gpu/drm/amd/amdgpu/amdgpu_display.c "can't create framebuffer\n", mode_cmd->handles[0]); mode_cmd 569 drivers/gpu/drm/amd/amdgpu/amdgpu_display.c ret = amdgpu_display_framebuffer_init(dev, amdgpu_fb, mode_cmd, obj); mode_cmd 46 drivers/gpu/drm/amd/amdgpu/amdgpu_display.h const struct drm_mode_fb_cmd2 *mode_cmd); mode_cmd 121 drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c struct drm_mode_fb_cmd2 *mode_cmd, mode_cmd 132 drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c int height = mode_cmd->height; mode_cmd 138 drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c info = drm_get_format_info(adev->ddev, mode_cmd); mode_cmd 142 drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c mode_cmd->pitches[0] = amdgpu_align_pitch(adev, mode_cmd->width, cpp, mode_cmd 145 drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c height = ALIGN(mode_cmd->height, 8); mode_cmd 146 drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c size = mode_cmd->pitches[0] * height; mode_cmd 204 drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c struct drm_mode_fb_cmd2 mode_cmd; mode_cmd 210 drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c mode_cmd.width = sizes->surface_width; mode_cmd 211 drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c mode_cmd.height = sizes->surface_height; mode_cmd 216 drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c mode_cmd.pixel_format = drm_mode_legacy_fb_format(sizes->surface_bpp, mode_cmd 219 drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c ret = amdgpufb_create_pinned_object(rfbdev, &mode_cmd, &gobj); mode_cmd 235 drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c &mode_cmd, gobj); mode_cmd 601 drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h const struct drm_mode_fb_cmd2 *mode_cmd, mode_cmd 41 drivers/gpu/drm/arm/display/komeda/komeda_framebuffer.c const struct drm_mode_fb_cmd2 *mode_cmd) mode_cmd 49 drivers/gpu/drm/arm/display/komeda/komeda_framebuffer.c obj = drm_gem_object_lookup(file, mode_cmd->handles[0]); mode_cmd 113 drivers/gpu/drm/arm/display/komeda/komeda_framebuffer.c const struct drm_mode_fb_cmd2 *mode_cmd) mode_cmd 125 drivers/gpu/drm/arm/display/komeda/komeda_framebuffer.c obj = drm_gem_object_lookup(file, mode_cmd->handles[i]); mode_cmd 160 drivers/gpu/drm/arm/display/komeda/komeda_framebuffer.c const struct drm_mode_fb_cmd2 *mode_cmd) mode_cmd 171 drivers/gpu/drm/arm/display/komeda/komeda_framebuffer.c mode_cmd->pixel_format, mode_cmd 172 drivers/gpu/drm/arm/display/komeda/komeda_framebuffer.c mode_cmd->modifier[0]); mode_cmd 175 drivers/gpu/drm/arm/display/komeda/komeda_framebuffer.c mode_cmd->pixel_format); mode_cmd 180 drivers/gpu/drm/arm/display/komeda/komeda_framebuffer.c drm_helper_mode_fill_fb_struct(dev, &kfb->base, mode_cmd); mode_cmd 183 drivers/gpu/drm/arm/display/komeda/komeda_framebuffer.c ret = komeda_fb_afbc_size_check(kfb, file, mode_cmd); mode_cmd 185 drivers/gpu/drm/arm/display/komeda/komeda_framebuffer.c ret = komeda_fb_none_afbc_size_check(mdev, kfb, file, mode_cmd); mode_cmd 40 drivers/gpu/drm/arm/display/komeda/komeda_framebuffer.h const struct drm_mode_fb_cmd2 *mode_cmd); mode_cmd 274 drivers/gpu/drm/arm/malidp_drv.c const struct drm_mode_fb_cmd2 *mode_cmd) mode_cmd 276 drivers/gpu/drm/arm/malidp_drv.c if (malidp_format_mod_supported(dev, mode_cmd->pixel_format, mode_cmd 277 drivers/gpu/drm/arm/malidp_drv.c mode_cmd->modifier[0]) == false) mode_cmd 280 drivers/gpu/drm/arm/malidp_drv.c if (mode_cmd->offsets[0] != 0) { mode_cmd 285 drivers/gpu/drm/arm/malidp_drv.c switch (mode_cmd->modifier[0] & AFBC_SIZE_MASK) { mode_cmd 287 drivers/gpu/drm/arm/malidp_drv.c if ((mode_cmd->width % 16) || (mode_cmd->height % 16)) { mode_cmd 303 drivers/gpu/drm/arm/malidp_drv.c const struct drm_mode_fb_cmd2 *mode_cmd) mode_cmd 312 drivers/gpu/drm/arm/malidp_drv.c switch (mode_cmd->modifier[0] & AFBC_SIZE_MASK) { mode_cmd 322 drivers/gpu/drm/arm/malidp_drv.c info = drm_get_format_info(dev, mode_cmd); mode_cmd 324 drivers/gpu/drm/arm/malidp_drv.c n_superblocks = (mode_cmd->width / afbc_superblock_width) * mode_cmd 325 drivers/gpu/drm/arm/malidp_drv.c (mode_cmd->height / afbc_superblock_height); mode_cmd 335 drivers/gpu/drm/arm/malidp_drv.c if ((mode_cmd->width * bpp) != (mode_cmd->pitches[0] * BITS_PER_BYTE)) { mode_cmd 338 drivers/gpu/drm/arm/malidp_drv.c (mode_cmd->pitches[0] * BITS_PER_BYTE), mode_cmd 339 drivers/gpu/drm/arm/malidp_drv.c mode_cmd->width, bpp); mode_cmd 343 drivers/gpu/drm/arm/malidp_drv.c objs = drm_gem_object_lookup(file, mode_cmd->handles[0]); mode_cmd 363 drivers/gpu/drm/arm/malidp_drv.c const struct drm_mode_fb_cmd2 *mode_cmd) mode_cmd 365 drivers/gpu/drm/arm/malidp_drv.c if (malidp_verify_afbc_framebuffer_caps(dev, mode_cmd)) mode_cmd 366 drivers/gpu/drm/arm/malidp_drv.c return malidp_verify_afbc_framebuffer_size(dev, file, mode_cmd); mode_cmd 373 drivers/gpu/drm/arm/malidp_drv.c const struct drm_mode_fb_cmd2 *mode_cmd) mode_cmd 375 drivers/gpu/drm/arm/malidp_drv.c if (mode_cmd->modifier[0]) { mode_cmd 376 drivers/gpu/drm/arm/malidp_drv.c if (!malidp_verify_afbc_framebuffer(dev, file, mode_cmd)) mode_cmd 380 drivers/gpu/drm/arm/malidp_drv.c return drm_gem_fb_create(dev, file, mode_cmd); mode_cmd 561 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c struct drm_file *file_priv, const struct drm_mode_fb_cmd2 *mode_cmd) mode_cmd 563 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c return drm_gem_fb_create(dev, file_priv, mode_cmd); mode_cmd 171 drivers/gpu/drm/bochs/bochs_kms.c const struct drm_mode_fb_cmd2 *mode_cmd) mode_cmd 173 drivers/gpu/drm/bochs/bochs_kms.c if (mode_cmd->pixel_format != DRM_FORMAT_XRGB8888 && mode_cmd 174 drivers/gpu/drm/bochs/bochs_kms.c mode_cmd->pixel_format != DRM_FORMAT_BGRX8888) mode_cmd 177 drivers/gpu/drm/bochs/bochs_kms.c return drm_gem_fb_create(dev, file, mode_cmd); mode_cmd 480 drivers/gpu/drm/cirrus/cirrus.c const struct drm_mode_fb_cmd2 *mode_cmd) mode_cmd 482 drivers/gpu/drm/cirrus/cirrus.c if (mode_cmd->pixel_format != DRM_FORMAT_RGB565 && mode_cmd 483 drivers/gpu/drm/cirrus/cirrus.c mode_cmd->pixel_format != DRM_FORMAT_RGB888 && mode_cmd 484 drivers/gpu/drm/cirrus/cirrus.c mode_cmd->pixel_format != DRM_FORMAT_XRGB8888) mode_cmd 486 drivers/gpu/drm/cirrus/cirrus.c if (cirrus_check_size(mode_cmd->width, mode_cmd->height, NULL) < 0) mode_cmd 488 drivers/gpu/drm/cirrus/cirrus.c return drm_gem_fb_create_with_dirty(dev, file_priv, mode_cmd); mode_cmd 189 drivers/gpu/drm/cirrus/cirrus_drv.h const struct drm_mode_fb_cmd2 *mode_cmd, mode_cmd 321 drivers/gpu/drm/drm_fourcc.c const struct drm_mode_fb_cmd2 *mode_cmd) mode_cmd 326 drivers/gpu/drm/drm_fourcc.c info = dev->mode_config.funcs->get_format_info(mode_cmd); mode_cmd 329 drivers/gpu/drm/drm_fourcc.c info = drm_format_info(mode_cmd->pixel_format); mode_cmd 59 drivers/gpu/drm/drm_gem_framebuffer_helper.c const struct drm_mode_fb_cmd2 *mode_cmd, mode_cmd 70 drivers/gpu/drm/drm_gem_framebuffer_helper.c drm_helper_mode_fill_fb_struct(dev, fb, mode_cmd); mode_cmd 144 drivers/gpu/drm/drm_gem_framebuffer_helper.c const struct drm_mode_fb_cmd2 *mode_cmd, mode_cmd 152 drivers/gpu/drm/drm_gem_framebuffer_helper.c info = drm_get_format_info(dev, mode_cmd); mode_cmd 157 drivers/gpu/drm/drm_gem_framebuffer_helper.c unsigned int width = mode_cmd->width / (i ? info->hsub : 1); mode_cmd 158 drivers/gpu/drm/drm_gem_framebuffer_helper.c unsigned int height = mode_cmd->height / (i ? info->vsub : 1); mode_cmd 161 drivers/gpu/drm/drm_gem_framebuffer_helper.c objs[i] = drm_gem_object_lookup(file, mode_cmd->handles[i]); mode_cmd 168 drivers/gpu/drm/drm_gem_framebuffer_helper.c min_size = (height - 1) * mode_cmd->pitches[i] mode_cmd 170 drivers/gpu/drm/drm_gem_framebuffer_helper.c + mode_cmd->offsets[i]; mode_cmd 179 drivers/gpu/drm/drm_gem_framebuffer_helper.c fb = drm_gem_fb_alloc(dev, mode_cmd, objs, i, funcs); mode_cmd 224 drivers/gpu/drm/drm_gem_framebuffer_helper.c const struct drm_mode_fb_cmd2 *mode_cmd) mode_cmd 226 drivers/gpu/drm/drm_gem_framebuffer_helper.c return drm_gem_fb_create_with_funcs(dev, file, mode_cmd, mode_cmd 262 drivers/gpu/drm/drm_gem_framebuffer_helper.c const struct drm_mode_fb_cmd2 *mode_cmd) mode_cmd 264 drivers/gpu/drm/drm_gem_framebuffer_helper.c return drm_gem_fb_create_with_funcs(dev, file, mode_cmd, mode_cmd 81 drivers/gpu/drm/drm_modeset_helper.c const struct drm_mode_fb_cmd2 *mode_cmd) mode_cmd 86 drivers/gpu/drm/drm_modeset_helper.c fb->format = drm_get_format_info(dev, mode_cmd); mode_cmd 87 drivers/gpu/drm/drm_modeset_helper.c fb->width = mode_cmd->width; mode_cmd 88 drivers/gpu/drm/drm_modeset_helper.c fb->height = mode_cmd->height; mode_cmd 90 drivers/gpu/drm/drm_modeset_helper.c fb->pitches[i] = mode_cmd->pitches[i]; mode_cmd 91 drivers/gpu/drm/drm_modeset_helper.c fb->offsets[i] = mode_cmd->offsets[i]; mode_cmd 93 drivers/gpu/drm/drm_modeset_helper.c fb->modifier = mode_cmd->modifier[0]; mode_cmd 94 drivers/gpu/drm/drm_modeset_helper.c fb->flags = mode_cmd->flags; mode_cmd 59 drivers/gpu/drm/exynos/exynos_drm_fb.c const struct drm_mode_fb_cmd2 *mode_cmd, mode_cmd 79 drivers/gpu/drm/exynos/exynos_drm_fb.c drm_helper_mode_fill_fb_struct(dev, fb, mode_cmd); mode_cmd 97 drivers/gpu/drm/exynos/exynos_drm_fb.c const struct drm_mode_fb_cmd2 *mode_cmd) mode_cmd 99 drivers/gpu/drm/exynos/exynos_drm_fb.c const struct drm_format_info *info = drm_get_format_info(dev, mode_cmd); mode_cmd 106 drivers/gpu/drm/exynos/exynos_drm_fb.c unsigned int height = (i == 0) ? mode_cmd->height : mode_cmd 107 drivers/gpu/drm/exynos/exynos_drm_fb.c DIV_ROUND_UP(mode_cmd->height, info->vsub); mode_cmd 108 drivers/gpu/drm/exynos/exynos_drm_fb.c unsigned long size = height * mode_cmd->pitches[i] + mode_cmd 109 drivers/gpu/drm/exynos/exynos_drm_fb.c mode_cmd->offsets[i]; mode_cmd 112 drivers/gpu/drm/exynos/exynos_drm_fb.c mode_cmd->handles[i]); mode_cmd 127 drivers/gpu/drm/exynos/exynos_drm_fb.c fb = exynos_drm_framebuffer_init(dev, mode_cmd, exynos_gem, i); mode_cmd 17 drivers/gpu/drm/exynos/exynos_drm_fb.h const struct drm_mode_fb_cmd2 *mode_cmd, mode_cmd 119 drivers/gpu/drm/exynos/exynos_drm_fbdev.c struct drm_mode_fb_cmd2 mode_cmd = { 0 }; mode_cmd 128 drivers/gpu/drm/exynos/exynos_drm_fbdev.c mode_cmd.width = sizes->surface_width; mode_cmd 129 drivers/gpu/drm/exynos/exynos_drm_fbdev.c mode_cmd.height = sizes->surface_height; mode_cmd 130 drivers/gpu/drm/exynos/exynos_drm_fbdev.c mode_cmd.pitches[0] = sizes->surface_width * (sizes->surface_bpp >> 3); mode_cmd 131 drivers/gpu/drm/exynos/exynos_drm_fbdev.c mode_cmd.pixel_format = drm_mode_legacy_fb_format(sizes->surface_bpp, mode_cmd 134 drivers/gpu/drm/exynos/exynos_drm_fbdev.c size = mode_cmd.pitches[0] * mode_cmd.height; mode_cmd 154 drivers/gpu/drm/exynos/exynos_drm_fbdev.c exynos_drm_framebuffer_init(dev, &mode_cmd, &exynos_gem, 1); mode_cmd 213 drivers/gpu/drm/gma500/framebuffer.c const struct drm_mode_fb_cmd2 *mode_cmd, mode_cmd 223 drivers/gpu/drm/gma500/framebuffer.c info = drm_get_format_info(dev, mode_cmd); mode_cmd 227 drivers/gpu/drm/gma500/framebuffer.c if (mode_cmd->pitches[0] & 63) mode_cmd 230 drivers/gpu/drm/gma500/framebuffer.c drm_helper_mode_fill_fb_struct(dev, &fb->base, mode_cmd); mode_cmd 254 drivers/gpu/drm/gma500/framebuffer.c const struct drm_mode_fb_cmd2 *mode_cmd, mode_cmd 264 drivers/gpu/drm/gma500/framebuffer.c ret = psb_framebuffer_init(dev, fb, mode_cmd, gt); mode_cmd 311 drivers/gpu/drm/gma500/framebuffer.c struct drm_mode_fb_cmd2 mode_cmd; mode_cmd 319 drivers/gpu/drm/gma500/framebuffer.c mode_cmd.width = sizes->surface_width; mode_cmd 320 drivers/gpu/drm/gma500/framebuffer.c mode_cmd.height = sizes->surface_height; mode_cmd 334 drivers/gpu/drm/gma500/framebuffer.c mode_cmd.pitches[0] = ALIGN(mode_cmd.width * ((bpp + 7) / 8), 4096 >> pitch_lines); mode_cmd 336 drivers/gpu/drm/gma500/framebuffer.c size = mode_cmd.pitches[0] * mode_cmd.height; mode_cmd 362 drivers/gpu/drm/gma500/framebuffer.c mode_cmd.pitches[0] = ALIGN(mode_cmd.width * ((bpp + 7) / 8), 64); mode_cmd 364 drivers/gpu/drm/gma500/framebuffer.c size = mode_cmd.pitches[0] * mode_cmd.height; mode_cmd 381 drivers/gpu/drm/gma500/framebuffer.c mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth); mode_cmd 383 drivers/gpu/drm/gma500/framebuffer.c ret = psb_framebuffer_init(dev, psbfb, &mode_cmd, backing); mode_cmd 66 drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_drv.h const struct drm_mode_fb_cmd2 *mode_cmd, mode_cmd 24 drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_fbdev.c const struct drm_mode_fb_cmd2 *mode_cmd, mode_cmd 32 drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_fbdev.c size = mode_cmd->pitches[0] * mode_cmd->height; mode_cmd 60 drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_fbdev.c struct drm_mode_fb_cmd2 mode_cmd; mode_cmd 74 drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_fbdev.c mode_cmd.width = sizes->surface_width; mode_cmd 75 drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_fbdev.c mode_cmd.height = sizes->surface_height; mode_cmd 76 drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_fbdev.c mode_cmd.pitches[0] = mode_cmd.width * bytes_per_pixel; mode_cmd 77 drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_fbdev.c mode_cmd.pixel_format = drm_mode_legacy_fb_format(sizes->surface_bpp, mode_cmd 80 drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_fbdev.c size = PAGE_ALIGN(mode_cmd.pitches[0] * mode_cmd.height); mode_cmd 82 drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_fbdev.c ret = hibmcfb_create_object(priv, &mode_cmd, &gobj); mode_cmd 110 drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_fbdev.c hi_fbdev->fb = hibmc_framebuffer_init(priv->dev, &mode_cmd, gobj); mode_cmd 116 drivers/gpu/drm/hisilicon/hibmc/hibmc_ttm.c const struct drm_mode_fb_cmd2 *mode_cmd, mode_cmd 128 drivers/gpu/drm/hisilicon/hibmc/hibmc_ttm.c drm_helper_mode_fill_fb_struct(dev, &hibmc_fb->fb, mode_cmd); mode_cmd 143 drivers/gpu/drm/hisilicon/hibmc/hibmc_ttm.c const struct drm_mode_fb_cmd2 *mode_cmd) mode_cmd 149 drivers/gpu/drm/hisilicon/hibmc/hibmc_ttm.c mode_cmd->width, mode_cmd->height, mode_cmd 150 drivers/gpu/drm/hisilicon/hibmc/hibmc_ttm.c (mode_cmd->pixel_format) & 0xff, mode_cmd 151 drivers/gpu/drm/hisilicon/hibmc/hibmc_ttm.c (mode_cmd->pixel_format >> 8) & 0xff, mode_cmd 152 drivers/gpu/drm/hisilicon/hibmc/hibmc_ttm.c (mode_cmd->pixel_format >> 16) & 0xff, mode_cmd 153 drivers/gpu/drm/hisilicon/hibmc/hibmc_ttm.c (mode_cmd->pixel_format >> 24) & 0xff); mode_cmd 155 drivers/gpu/drm/hisilicon/hibmc/hibmc_ttm.c obj = drm_gem_object_lookup(filp, mode_cmd->handles[0]); mode_cmd 159 drivers/gpu/drm/hisilicon/hibmc/hibmc_ttm.c hibmc_fb = hibmc_framebuffer_init(dev, mode_cmd, obj); mode_cmd 124 drivers/gpu/drm/i915/display/intel_display.c struct drm_mode_fb_cmd2 *mode_cmd); mode_cmd 3039 drivers/gpu/drm/i915/display/intel_display.c struct drm_mode_fb_cmd2 mode_cmd = { 0 }; mode_cmd 3090 drivers/gpu/drm/i915/display/intel_display.c mode_cmd.pixel_format = fb->format->format; mode_cmd 3091 drivers/gpu/drm/i915/display/intel_display.c mode_cmd.width = fb->width; mode_cmd 3092 drivers/gpu/drm/i915/display/intel_display.c mode_cmd.height = fb->height; mode_cmd 3093 drivers/gpu/drm/i915/display/intel_display.c mode_cmd.pitches[0] = fb->pitches[0]; mode_cmd 3094 drivers/gpu/drm/i915/display/intel_display.c mode_cmd.modifier[0] = fb->modifier; mode_cmd 3095 drivers/gpu/drm/i915/display/intel_display.c mode_cmd.flags = DRM_MODE_FB_MODIFIERS; mode_cmd 3097 drivers/gpu/drm/i915/display/intel_display.c if (intel_framebuffer_init(to_intel_framebuffer(fb), obj, &mode_cmd)) { mode_cmd 11041 drivers/gpu/drm/i915/display/intel_display.c struct drm_mode_fb_cmd2 *mode_cmd) mode_cmd 11050 drivers/gpu/drm/i915/display/intel_display.c ret = intel_framebuffer_init(intel_fb, obj, mode_cmd); mode_cmd 15594 drivers/gpu/drm/i915/display/intel_display.c struct drm_mode_fb_cmd2 *mode_cmd) mode_cmd 15612 drivers/gpu/drm/i915/display/intel_display.c if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) { mode_cmd 15618 drivers/gpu/drm/i915/display/intel_display.c tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) { mode_cmd 15624 drivers/gpu/drm/i915/display/intel_display.c mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED; mode_cmd 15632 drivers/gpu/drm/i915/display/intel_display.c mode_cmd->pixel_format, mode_cmd 15633 drivers/gpu/drm/i915/display/intel_display.c mode_cmd->modifier[0])) { mode_cmd 15637 drivers/gpu/drm/i915/display/intel_display.c drm_get_format_name(mode_cmd->pixel_format, mode_cmd 15639 drivers/gpu/drm/i915/display/intel_display.c mode_cmd->modifier[0]); mode_cmd 15648 drivers/gpu/drm/i915/display/intel_display.c tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) { mode_cmd 15653 drivers/gpu/drm/i915/display/intel_display.c max_stride = intel_fb_max_stride(dev_priv, mode_cmd->pixel_format, mode_cmd 15654 drivers/gpu/drm/i915/display/intel_display.c mode_cmd->modifier[0]); mode_cmd 15655 drivers/gpu/drm/i915/display/intel_display.c if (mode_cmd->pitches[0] > max_stride) { mode_cmd 15657 drivers/gpu/drm/i915/display/intel_display.c mode_cmd->modifier[0] != DRM_FORMAT_MOD_LINEAR ? mode_cmd 15659 drivers/gpu/drm/i915/display/intel_display.c mode_cmd->pitches[0], max_stride); mode_cmd 15667 drivers/gpu/drm/i915/display/intel_display.c if (tiling != I915_TILING_NONE && mode_cmd->pitches[0] != stride) { mode_cmd 15669 drivers/gpu/drm/i915/display/intel_display.c mode_cmd->pitches[0], stride); mode_cmd 15674 drivers/gpu/drm/i915/display/intel_display.c if (mode_cmd->offsets[0] != 0) mode_cmd 15677 drivers/gpu/drm/i915/display/intel_display.c drm_helper_mode_fill_fb_struct(&dev_priv->drm, fb, mode_cmd); mode_cmd 15682 drivers/gpu/drm/i915/display/intel_display.c if (mode_cmd->handles[i] != mode_cmd->handles[0]) { mode_cmd 15735 drivers/gpu/drm/i915/display/intel_display.c struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd; mode_cmd 15737 drivers/gpu/drm/i915/display/intel_display.c obj = i915_gem_object_lookup(filp, mode_cmd.handles[0]); mode_cmd 15741 drivers/gpu/drm/i915/display/intel_display.c fb = intel_framebuffer_create(obj, &mode_cmd); mode_cmd 481 drivers/gpu/drm/i915/display/intel_display.h struct drm_mode_fb_cmd2 *mode_cmd); mode_cmd 122 drivers/gpu/drm/i915/display/intel_fbdev.c struct drm_mode_fb_cmd2 mode_cmd = {}; mode_cmd 130 drivers/gpu/drm/i915/display/intel_fbdev.c mode_cmd.width = sizes->surface_width; mode_cmd 131 drivers/gpu/drm/i915/display/intel_fbdev.c mode_cmd.height = sizes->surface_height; mode_cmd 133 drivers/gpu/drm/i915/display/intel_fbdev.c mode_cmd.pitches[0] = ALIGN(mode_cmd.width * mode_cmd 135 drivers/gpu/drm/i915/display/intel_fbdev.c mode_cmd.pixel_format = drm_mode_legacy_fb_format(sizes->surface_bpp, mode_cmd 138 drivers/gpu/drm/i915/display/intel_fbdev.c size = mode_cmd.pitches[0] * mode_cmd.height; mode_cmd 154 drivers/gpu/drm/i915/display/intel_fbdev.c fb = intel_framebuffer_create(obj, &mode_cmd); mode_cmd 338 drivers/gpu/drm/msm/msm_drv.h struct drm_file *file, const struct drm_mode_fb_cmd2 *mode_cmd); mode_cmd 25 drivers/gpu/drm/msm/msm_fb.c const struct drm_mode_fb_cmd2 *mode_cmd, struct drm_gem_object **bos); mode_cmd 100 drivers/gpu/drm/msm/msm_fb.c struct drm_file *file, const struct drm_mode_fb_cmd2 *mode_cmd) mode_cmd 103 drivers/gpu/drm/msm/msm_fb.c mode_cmd); mode_cmd 109 drivers/gpu/drm/msm/msm_fb.c bos[i] = drm_gem_object_lookup(file, mode_cmd->handles[i]); mode_cmd 116 drivers/gpu/drm/msm/msm_fb.c fb = msm_framebuffer_init(dev, mode_cmd, bos); mode_cmd 131 drivers/gpu/drm/msm/msm_fb.c const struct drm_mode_fb_cmd2 *mode_cmd, struct drm_gem_object **bos) mode_cmd 134 drivers/gpu/drm/msm/msm_fb.c mode_cmd); mode_cmd 143 drivers/gpu/drm/msm/msm_fb.c dev, mode_cmd, mode_cmd->width, mode_cmd->height, mode_cmd 144 drivers/gpu/drm/msm/msm_fb.c (char *)&mode_cmd->pixel_format); mode_cmd 147 drivers/gpu/drm/msm/msm_fb.c format = kms->funcs->get_format(kms, mode_cmd->pixel_format, mode_cmd 148 drivers/gpu/drm/msm/msm_fb.c mode_cmd->modifier[0]); mode_cmd 151 drivers/gpu/drm/msm/msm_fb.c (char *)&mode_cmd->pixel_format); mode_cmd 172 drivers/gpu/drm/msm/msm_fb.c unsigned int width = mode_cmd->width / (i ? info->hsub : 1); mode_cmd 173 drivers/gpu/drm/msm/msm_fb.c unsigned int height = mode_cmd->height / (i ? info->vsub : 1); mode_cmd 176 drivers/gpu/drm/msm/msm_fb.c min_size = (height - 1) * mode_cmd->pitches[i] mode_cmd 178 drivers/gpu/drm/msm/msm_fb.c + mode_cmd->offsets[i]; mode_cmd 188 drivers/gpu/drm/msm/msm_fb.c drm_helper_mode_fill_fb_struct(dev, fb, mode_cmd); mode_cmd 209 drivers/gpu/drm/msm/msm_fb.c struct drm_mode_fb_cmd2 mode_cmd = { mode_cmd 220 drivers/gpu/drm/msm/msm_fb.c size = mode_cmd.pitches[0] * mode_cmd.height; mode_cmd 235 drivers/gpu/drm/msm/msm_fb.c fb = msm_framebuffer_init(dev, &mode_cmd, &bo); mode_cmd 229 drivers/gpu/drm/nouveau/nouveau_display.c const struct drm_mode_fb_cmd2 *mode_cmd, mode_cmd 240 drivers/gpu/drm/nouveau/nouveau_display.c (mode_cmd->pixel_format == DRM_FORMAT_YUYV || mode_cmd 241 drivers/gpu/drm/nouveau/nouveau_display.c mode_cmd->pixel_format == DRM_FORMAT_UYVY || mode_cmd 242 drivers/gpu/drm/nouveau/nouveau_display.c mode_cmd->pixel_format == DRM_FORMAT_NV12 || mode_cmd 243 drivers/gpu/drm/nouveau/nouveau_display.c mode_cmd->pixel_format == DRM_FORMAT_NV21) && mode_cmd 244 drivers/gpu/drm/nouveau/nouveau_display.c (mode_cmd->pitches[0] & 0x3f || /* align 64 */ mode_cmd 245 drivers/gpu/drm/nouveau/nouveau_display.c mode_cmd->pitches[0] >= 0x10000 || /* at most 64k pitch */ mode_cmd 246 drivers/gpu/drm/nouveau/nouveau_display.c (mode_cmd->pitches[1] && /* pitches for planes must match */ mode_cmd 247 drivers/gpu/drm/nouveau/nouveau_display.c mode_cmd->pitches[0] != mode_cmd->pitches[1]))) { mode_cmd 250 drivers/gpu/drm/nouveau/nouveau_display.c drm_get_format_name(mode_cmd->pixel_format, mode_cmd 252 drivers/gpu/drm/nouveau/nouveau_display.c mode_cmd->pitches[0], mode_cmd 253 drivers/gpu/drm/nouveau/nouveau_display.c mode_cmd->pitches[1]); mode_cmd 260 drivers/gpu/drm/nouveau/nouveau_display.c drm_helper_mode_fill_fb_struct(dev, &fb->base, mode_cmd); mode_cmd 272 drivers/gpu/drm/nouveau/nouveau_display.c const struct drm_mode_fb_cmd2 *mode_cmd) mode_cmd 279 drivers/gpu/drm/nouveau/nouveau_display.c gem = drm_gem_object_lookup(file_priv, mode_cmd->handles[0]); mode_cmd 284 drivers/gpu/drm/nouveau/nouveau_display.c ret = nouveau_framebuffer_new(dev, mode_cmd, nvbo, &fb); mode_cmd 318 drivers/gpu/drm/nouveau/nouveau_fbcon.c struct drm_mode_fb_cmd2 mode_cmd; mode_cmd 321 drivers/gpu/drm/nouveau/nouveau_fbcon.c mode_cmd.width = sizes->surface_width; mode_cmd 322 drivers/gpu/drm/nouveau/nouveau_fbcon.c mode_cmd.height = sizes->surface_height; mode_cmd 324 drivers/gpu/drm/nouveau/nouveau_fbcon.c mode_cmd.pitches[0] = mode_cmd.width * (sizes->surface_bpp >> 3); mode_cmd 325 drivers/gpu/drm/nouveau/nouveau_fbcon.c mode_cmd.pitches[0] = roundup(mode_cmd.pitches[0], 256); mode_cmd 327 drivers/gpu/drm/nouveau/nouveau_fbcon.c mode_cmd.pixel_format = drm_mode_legacy_fb_format(sizes->surface_bpp, mode_cmd 330 drivers/gpu/drm/nouveau/nouveau_fbcon.c ret = nouveau_gem_new(&drm->client, mode_cmd.pitches[0] * mode_cmd 331 drivers/gpu/drm/nouveau/nouveau_fbcon.c mode_cmd.height, 0, NOUVEAU_GEM_DOMAIN_VRAM, mode_cmd 338 drivers/gpu/drm/nouveau/nouveau_fbcon.c ret = nouveau_framebuffer_new(dev, &mode_cmd, nvbo, &fb); mode_cmd 307 drivers/gpu/drm/omapdrm/omap_fb.c struct drm_file *file, const struct drm_mode_fb_cmd2 *mode_cmd) mode_cmd 310 drivers/gpu/drm/omapdrm/omap_fb.c mode_cmd); mode_cmd 317 drivers/gpu/drm/omapdrm/omap_fb.c bos[i] = drm_gem_object_lookup(file, mode_cmd->handles[i]); mode_cmd 324 drivers/gpu/drm/omapdrm/omap_fb.c fb = omap_framebuffer_init(dev, mode_cmd, bos); mode_cmd 338 drivers/gpu/drm/omapdrm/omap_fb.c const struct drm_mode_fb_cmd2 *mode_cmd, struct drm_gem_object **bos) mode_cmd 343 drivers/gpu/drm/omapdrm/omap_fb.c unsigned int pitch = mode_cmd->pitches[0]; mode_cmd 347 drivers/gpu/drm/omapdrm/omap_fb.c dev, mode_cmd, mode_cmd->width, mode_cmd->height, mode_cmd 348 drivers/gpu/drm/omapdrm/omap_fb.c (char *)&mode_cmd->pixel_format); mode_cmd 350 drivers/gpu/drm/omapdrm/omap_fb.c format = drm_get_format_info(dev, mode_cmd); mode_cmd 353 drivers/gpu/drm/omapdrm/omap_fb.c if (formats[i] == mode_cmd->pixel_format) mode_cmd 359 drivers/gpu/drm/omapdrm/omap_fb.c (char *)&mode_cmd->pixel_format); mode_cmd 379 drivers/gpu/drm/omapdrm/omap_fb.c if (format->num_planes == 2 && pitch != mode_cmd->pitches[1]) { mode_cmd 398 drivers/gpu/drm/omapdrm/omap_fb.c size = pitch * mode_cmd->height / vsub; mode_cmd 400 drivers/gpu/drm/omapdrm/omap_fb.c if (size > omap_gem_mmap_size(bos[i]) - mode_cmd->offsets[i]) { mode_cmd 403 drivers/gpu/drm/omapdrm/omap_fb.c bos[i]->size - mode_cmd->offsets[i], size); mode_cmd 412 drivers/gpu/drm/omapdrm/omap_fb.c drm_helper_mode_fill_fb_struct(dev, fb, mode_cmd); mode_cmd 23 drivers/gpu/drm/omapdrm/omap_fb.h struct drm_file *file, const struct drm_mode_fb_cmd2 *mode_cmd); mode_cmd 25 drivers/gpu/drm/omapdrm/omap_fb.h const struct drm_mode_fb_cmd2 *mode_cmd, struct drm_gem_object **bos); mode_cmd 99 drivers/gpu/drm/omapdrm/omap_fbdev.c struct drm_mode_fb_cmd2 mode_cmd = {0}; mode_cmd 110 drivers/gpu/drm/omapdrm/omap_fbdev.c mode_cmd.pixel_format = drm_mode_legacy_fb_format(sizes->surface_bpp, mode_cmd 113 drivers/gpu/drm/omapdrm/omap_fbdev.c mode_cmd.width = sizes->surface_width; mode_cmd 114 drivers/gpu/drm/omapdrm/omap_fbdev.c mode_cmd.height = sizes->surface_height; mode_cmd 116 drivers/gpu/drm/omapdrm/omap_fbdev.c mode_cmd.pitches[0] = mode_cmd 117 drivers/gpu/drm/omapdrm/omap_fbdev.c DIV_ROUND_UP(mode_cmd.width * sizes->surface_bpp, 8); mode_cmd 122 drivers/gpu/drm/omapdrm/omap_fbdev.c mode_cmd.pitches[0] = PAGE_ALIGN(mode_cmd.pitches[0]); mode_cmd 127 drivers/gpu/drm/omapdrm/omap_fbdev.c .bytes = PAGE_ALIGN(mode_cmd.pitches[0] * mode_cmd.height), mode_cmd 137 drivers/gpu/drm/omapdrm/omap_fbdev.c fb = omap_framebuffer_init(dev, &mode_cmd, &fbdev->bo); mode_cmd 1138 drivers/gpu/drm/qxl/qxl_display.c const struct drm_mode_fb_cmd2 *mode_cmd) mode_cmd 1140 drivers/gpu/drm/qxl/qxl_display.c return drm_gem_fb_create_with_funcs(dev, file_priv, mode_cmd, mode_cmd 1301 drivers/gpu/drm/radeon/radeon_display.c const struct drm_mode_fb_cmd2 *mode_cmd, mode_cmd 1306 drivers/gpu/drm/radeon/radeon_display.c drm_helper_mode_fill_fb_struct(dev, fb, mode_cmd); mode_cmd 1318 drivers/gpu/drm/radeon/radeon_display.c const struct drm_mode_fb_cmd2 *mode_cmd) mode_cmd 1324 drivers/gpu/drm/radeon/radeon_display.c obj = drm_gem_object_lookup(file_priv, mode_cmd->handles[0]); mode_cmd 1327 drivers/gpu/drm/radeon/radeon_display.c "can't create framebuffer\n", mode_cmd->handles[0]); mode_cmd 1343 drivers/gpu/drm/radeon/radeon_display.c ret = radeon_framebuffer_init(dev, fb, mode_cmd, obj); mode_cmd 126 drivers/gpu/drm/radeon/radeon_fb.c struct drm_mode_fb_cmd2 *mode_cmd, mode_cmd 137 drivers/gpu/drm/radeon/radeon_fb.c int height = mode_cmd->height; mode_cmd 140 drivers/gpu/drm/radeon/radeon_fb.c info = drm_get_format_info(rdev->ddev, mode_cmd); mode_cmd 144 drivers/gpu/drm/radeon/radeon_fb.c mode_cmd->pitches[0] = radeon_align_pitch(rdev, mode_cmd->width, cpp, mode_cmd 148 drivers/gpu/drm/radeon/radeon_fb.c height = ALIGN(mode_cmd->height, 8); mode_cmd 149 drivers/gpu/drm/radeon/radeon_fb.c size = mode_cmd->pitches[0] * height; mode_cmd 178 drivers/gpu/drm/radeon/radeon_fb.c mode_cmd->pitches[0]); mode_cmd 219 drivers/gpu/drm/radeon/radeon_fb.c struct drm_mode_fb_cmd2 mode_cmd; mode_cmd 225 drivers/gpu/drm/radeon/radeon_fb.c mode_cmd.width = sizes->surface_width; mode_cmd 226 drivers/gpu/drm/radeon/radeon_fb.c mode_cmd.height = sizes->surface_height; mode_cmd 232 drivers/gpu/drm/radeon/radeon_fb.c mode_cmd.pixel_format = drm_mode_legacy_fb_format(sizes->surface_bpp, mode_cmd 235 drivers/gpu/drm/radeon/radeon_fb.c ret = radeonfb_create_pinned_object(rfbdev, &mode_cmd, &gobj); mode_cmd 253 drivers/gpu/drm/radeon/radeon_fb.c ret = radeon_framebuffer_init(rdev->ddev, &rfbdev->fb, &mode_cmd, gobj); mode_cmd 930 drivers/gpu/drm/radeon/radeon_mode.h const struct drm_mode_fb_cmd2 *mode_cmd, mode_cmd 308 drivers/gpu/drm/rcar-du/rcar_du_kms.c const struct drm_mode_fb_cmd2 *mode_cmd) mode_cmd 316 drivers/gpu/drm/rcar-du/rcar_du_kms.c format = rcar_du_format_info(mode_cmd->pixel_format); mode_cmd 319 drivers/gpu/drm/rcar-du/rcar_du_kms.c mode_cmd->pixel_format); mode_cmd 347 drivers/gpu/drm/rcar-du/rcar_du_kms.c if (mode_cmd->pitches[0] & (align - 1) || mode_cmd 348 drivers/gpu/drm/rcar-du/rcar_du_kms.c mode_cmd->pitches[0] > max_pitch) { mode_cmd 350 drivers/gpu/drm/rcar-du/rcar_du_kms.c mode_cmd->pitches[0]); mode_cmd 355 drivers/gpu/drm/rcar-du/rcar_du_kms.c if (mode_cmd->pitches[i] != mode_cmd->pitches[0]) { mode_cmd 362 drivers/gpu/drm/rcar-du/rcar_du_kms.c return drm_gem_fb_create(dev, file_priv, mode_cmd); mode_cmd 28 drivers/gpu/drm/rockchip/rockchip_drm_fb.c rockchip_fb_alloc(struct drm_device *dev, const struct drm_mode_fb_cmd2 *mode_cmd, mode_cmd 39 drivers/gpu/drm/rockchip/rockchip_drm_fb.c drm_helper_mode_fill_fb_struct(dev, fb, mode_cmd); mode_cmd 58 drivers/gpu/drm/rockchip/rockchip_drm_fb.c const struct drm_mode_fb_cmd2 *mode_cmd) mode_cmd 61 drivers/gpu/drm/rockchip/rockchip_drm_fb.c mode_cmd); mode_cmd 70 drivers/gpu/drm/rockchip/rockchip_drm_fb.c unsigned int width = mode_cmd->width / (i ? info->hsub : 1); mode_cmd 71 drivers/gpu/drm/rockchip/rockchip_drm_fb.c unsigned int height = mode_cmd->height / (i ? info->vsub : 1); mode_cmd 74 drivers/gpu/drm/rockchip/rockchip_drm_fb.c obj = drm_gem_object_lookup(file_priv, mode_cmd->handles[i]); mode_cmd 82 drivers/gpu/drm/rockchip/rockchip_drm_fb.c min_size = (height - 1) * mode_cmd->pitches[i] + mode_cmd 83 drivers/gpu/drm/rockchip/rockchip_drm_fb.c mode_cmd->offsets[i] + mode_cmd 94 drivers/gpu/drm/rockchip/rockchip_drm_fb.c fb = rockchip_fb_alloc(dev, mode_cmd, objs, i); mode_cmd 121 drivers/gpu/drm/rockchip/rockchip_drm_fb.c const struct drm_mode_fb_cmd2 *mode_cmd, mode_cmd 126 drivers/gpu/drm/rockchip/rockchip_drm_fb.c fb = rockchip_fb_alloc(dev, mode_cmd, &obj, 1); mode_cmd 12 drivers/gpu/drm/rockchip/rockchip_drm_fb.h const struct drm_mode_fb_cmd2 *mode_cmd, mode_cmd 43 drivers/gpu/drm/rockchip/rockchip_drm_fbdev.c struct drm_mode_fb_cmd2 mode_cmd = { 0 }; mode_cmd 55 drivers/gpu/drm/rockchip/rockchip_drm_fbdev.c mode_cmd.width = sizes->surface_width; mode_cmd 56 drivers/gpu/drm/rockchip/rockchip_drm_fbdev.c mode_cmd.height = sizes->surface_height; mode_cmd 57 drivers/gpu/drm/rockchip/rockchip_drm_fbdev.c mode_cmd.pitches[0] = sizes->surface_width * bytes_per_pixel; mode_cmd 58 drivers/gpu/drm/rockchip/rockchip_drm_fbdev.c mode_cmd.pixel_format = drm_mode_legacy_fb_format(sizes->surface_bpp, mode_cmd 61 drivers/gpu/drm/rockchip/rockchip_drm_fbdev.c size = mode_cmd.pitches[0] * mode_cmd.height; mode_cmd 76 drivers/gpu/drm/rockchip/rockchip_drm_fbdev.c helper->fb = rockchip_drm_framebuffer_init(dev, &mode_cmd, mode_cmd 308 drivers/gpu/drm/selftests/test-drm_framebuffer.c const struct drm_mode_fb_cmd2 *mode_cmd) mode_cmd 93 drivers/gpu/drm/shmobile/shmob_drm_kms.c const struct drm_mode_fb_cmd2 *mode_cmd) mode_cmd 97 drivers/gpu/drm/shmobile/shmob_drm_kms.c format = shmob_drm_format_info(mode_cmd->pixel_format); mode_cmd 100 drivers/gpu/drm/shmobile/shmob_drm_kms.c mode_cmd->pixel_format); mode_cmd 104 drivers/gpu/drm/shmobile/shmob_drm_kms.c if (mode_cmd->pitches[0] & 7 || mode_cmd->pitches[0] >= 65536) { mode_cmd 106 drivers/gpu/drm/shmobile/shmob_drm_kms.c mode_cmd->pitches[0]); mode_cmd 113 drivers/gpu/drm/shmobile/shmob_drm_kms.c if (mode_cmd->pitches[1] != mode_cmd->pitches[0] * chroma_cpp) { mode_cmd 120 drivers/gpu/drm/shmobile/shmob_drm_kms.c return drm_gem_fb_create(dev, file_priv, mode_cmd); mode_cmd 101 drivers/gpu/drm/tegra/fb.c const struct drm_mode_fb_cmd2 *mode_cmd, mode_cmd 113 drivers/gpu/drm/tegra/fb.c drm_helper_mode_fill_fb_struct(drm, fb, mode_cmd); mode_cmd 68 drivers/gpu/drm/tilcdc/tilcdc_drv.c struct drm_file *file_priv, const struct drm_mode_fb_cmd2 *mode_cmd) mode_cmd 70 drivers/gpu/drm/tilcdc/tilcdc_drv.c return drm_gem_fb_create(dev, file_priv, mode_cmd); mode_cmd 119 drivers/gpu/drm/udl/udl_drv.h const struct drm_mode_fb_cmd2 *mode_cmd); mode_cmd 338 drivers/gpu/drm/udl/udl_fb.c const struct drm_mode_fb_cmd2 *mode_cmd, mode_cmd 344 drivers/gpu/drm/udl/udl_fb.c drm_helper_mode_fill_fb_struct(dev, &ufb->base, mode_cmd); mode_cmd 358 drivers/gpu/drm/udl/udl_fb.c struct drm_mode_fb_cmd2 mode_cmd; mode_cmd 366 drivers/gpu/drm/udl/udl_fb.c mode_cmd.width = sizes->surface_width; mode_cmd 367 drivers/gpu/drm/udl/udl_fb.c mode_cmd.height = sizes->surface_height; mode_cmd 368 drivers/gpu/drm/udl/udl_fb.c mode_cmd.pitches[0] = mode_cmd.width * ((sizes->surface_bpp + 7) / 8); mode_cmd 370 drivers/gpu/drm/udl/udl_fb.c mode_cmd.pixel_format = drm_mode_legacy_fb_format(sizes->surface_bpp, mode_cmd 373 drivers/gpu/drm/udl/udl_fb.c size = mode_cmd.pitches[0] * mode_cmd.height; mode_cmd 392 drivers/gpu/drm/udl/udl_fb.c ret = udl_framebuffer_init(dev, &ufbdev->ufb, &mode_cmd, obj); mode_cmd 498 drivers/gpu/drm/udl/udl_fb.c const struct drm_mode_fb_cmd2 *mode_cmd) mode_cmd 505 drivers/gpu/drm/udl/udl_fb.c obj = drm_gem_object_lookup(file, mode_cmd->handles[0]); mode_cmd 509 drivers/gpu/drm/udl/udl_fb.c size = mode_cmd->pitches[0] * mode_cmd->height; mode_cmd 513 drivers/gpu/drm/udl/udl_fb.c DRM_ERROR("object size not sufficient for fb %d %zu %d %d\n", size, obj->size, mode_cmd->pitches[0], mode_cmd->height); mode_cmd 521 drivers/gpu/drm/udl/udl_fb.c ret = udl_framebuffer_init(dev, ufb, mode_cmd, to_udl_bo(obj)); mode_cmd 157 drivers/gpu/drm/vboxvideo/vbox_drv.h const struct drm_mode_fb_cmd2 *mode_cmd, mode_cmd 50 drivers/gpu/drm/vboxvideo/vbox_fb.c struct drm_mode_fb_cmd2 mode_cmd; mode_cmd 59 drivers/gpu/drm/vboxvideo/vbox_fb.c mode_cmd.width = sizes->surface_width; mode_cmd 60 drivers/gpu/drm/vboxvideo/vbox_fb.c mode_cmd.height = sizes->surface_height; mode_cmd 61 drivers/gpu/drm/vboxvideo/vbox_fb.c pitch = mode_cmd.width * ((sizes->surface_bpp + 7) / 8); mode_cmd 62 drivers/gpu/drm/vboxvideo/vbox_fb.c mode_cmd.pixel_format = drm_mode_legacy_fb_format(sizes->surface_bpp, mode_cmd 64 drivers/gpu/drm/vboxvideo/vbox_fb.c mode_cmd.pitches[0] = pitch; mode_cmd 66 drivers/gpu/drm/vboxvideo/vbox_fb.c size = pitch * mode_cmd.height; mode_cmd 74 drivers/gpu/drm/vboxvideo/vbox_fb.c ret = vbox_framebuffer_init(vbox, &vbox->afb, &mode_cmd, gobj); mode_cmd 106 drivers/gpu/drm/vboxvideo/vbox_main.c const struct drm_mode_fb_cmd2 *mode_cmd, mode_cmd 111 drivers/gpu/drm/vboxvideo/vbox_main.c drm_helper_mode_fill_fb_struct(&vbox->ddev, &vbox_fb->base, mode_cmd); mode_cmd 862 drivers/gpu/drm/vboxvideo/vbox_mode.c const struct drm_mode_fb_cmd2 *mode_cmd) mode_cmd 870 drivers/gpu/drm/vboxvideo/vbox_mode.c obj = drm_gem_object_lookup(filp, mode_cmd->handles[0]); mode_cmd 878 drivers/gpu/drm/vboxvideo/vbox_mode.c ret = vbox_framebuffer_init(vbox, vbox_fb, mode_cmd, obj); mode_cmd 304 drivers/gpu/drm/vc4/vc4_kms.c const struct drm_mode_fb_cmd2 *mode_cmd) mode_cmd 311 drivers/gpu/drm/vc4/vc4_kms.c if (!(mode_cmd->flags & DRM_MODE_FB_MODIFIERS)) { mode_cmd 316 drivers/gpu/drm/vc4/vc4_kms.c mode_cmd->handles[0]); mode_cmd 319 drivers/gpu/drm/vc4/vc4_kms.c mode_cmd->handles[0]); mode_cmd 324 drivers/gpu/drm/vc4/vc4_kms.c mode_cmd_local = *mode_cmd; mode_cmd 335 drivers/gpu/drm/vc4/vc4_kms.c mode_cmd = &mode_cmd_local; mode_cmd 338 drivers/gpu/drm/vc4/vc4_kms.c return drm_gem_fb_create(dev, file_priv, mode_cmd); mode_cmd 65 drivers/gpu/drm/virtio/virtgpu_display.c const struct drm_mode_fb_cmd2 *mode_cmd, mode_cmd 72 drivers/gpu/drm/virtio/virtgpu_display.c drm_helper_mode_fill_fb_struct(dev, &vgfb->base, mode_cmd); mode_cmd 295 drivers/gpu/drm/virtio/virtgpu_display.c const struct drm_mode_fb_cmd2 *mode_cmd) mode_cmd 301 drivers/gpu/drm/virtio/virtgpu_display.c if (mode_cmd->pixel_format != DRM_FORMAT_HOST_XRGB8888 && mode_cmd 302 drivers/gpu/drm/virtio/virtgpu_display.c mode_cmd->pixel_format != DRM_FORMAT_HOST_ARGB8888) mode_cmd 306 drivers/gpu/drm/virtio/virtgpu_display.c obj = drm_gem_object_lookup(file_priv, mode_cmd->handles[0]); mode_cmd 314 drivers/gpu/drm/virtio/virtgpu_display.c ret = virtio_gpu_framebuffer_init(dev, virtio_gpu_fb, mode_cmd, obj); mode_cmd 331 drivers/gpu/drm/virtio/virtgpu_drv.h const struct drm_mode_fb_cmd2 *mode_cmd, mode_cmd 501 drivers/gpu/drm/vmwgfx/vmwgfx_fb.c struct drm_mode_fb_cmd2 mode_cmd; mode_cmd 513 drivers/gpu/drm/vmwgfx/vmwgfx_fb.c mode_cmd.width = var->xres; mode_cmd 514 drivers/gpu/drm/vmwgfx/vmwgfx_fb.c mode_cmd.height = var->yres; mode_cmd 515 drivers/gpu/drm/vmwgfx/vmwgfx_fb.c mode_cmd.pitches[0] = ((var->bits_per_pixel + 7) / 8) * mode_cmd.width; mode_cmd 516 drivers/gpu/drm/vmwgfx/vmwgfx_fb.c mode_cmd.pixel_format = mode_cmd 520 drivers/gpu/drm/vmwgfx/vmwgfx_fb.c if (cur_fb && cur_fb->width == mode_cmd.width && mode_cmd 521 drivers/gpu/drm/vmwgfx/vmwgfx_fb.c cur_fb->height == mode_cmd.height && mode_cmd 522 drivers/gpu/drm/vmwgfx/vmwgfx_fb.c cur_fb->format->format == mode_cmd.pixel_format && mode_cmd 523 drivers/gpu/drm/vmwgfx/vmwgfx_fb.c cur_fb->pitches[0] == mode_cmd.pitches[0]) mode_cmd 527 drivers/gpu/drm/vmwgfx/vmwgfx_fb.c new_bo_size = (size_t) mode_cmd.pitches[0] * (size_t) mode_cmd.height; mode_cmd 547 drivers/gpu/drm/vmwgfx/vmwgfx_fb.c true, &mode_cmd); mode_cmd 889 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c *mode_cmd, mode_cmd 913 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c surface->base_size.width < mode_cmd->width || mode_cmd 914 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c surface->base_size.height < mode_cmd->height || mode_cmd 921 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c switch (mode_cmd->pixel_format) { mode_cmd 936 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c drm_get_format_name(mode_cmd->pixel_format, &format_name)); mode_cmd 955 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c drm_helper_mode_fill_fb_struct(dev, &vfbs->base.base, mode_cmd); mode_cmd 957 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c vfbs->base.user_handle = mode_cmd->handles[0]; mode_cmd 1143 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c const struct drm_mode_fb_cmd2 *mode_cmd, mode_cmd 1154 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c switch (mode_cmd->pixel_format) { mode_cmd 1174 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c drm_get_format_name(mode_cmd->pixel_format, &format_name)); mode_cmd 1178 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c content_base_size.width = mode_cmd->pitches[0] / bytes_pp; mode_cmd 1179 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c content_base_size.height = mode_cmd->height; mode_cmd 1219 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c *mode_cmd) mode_cmd 1228 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c requested_size = mode_cmd->height * mode_cmd->pitches[0]; mode_cmd 1237 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c switch (mode_cmd->pixel_format) { mode_cmd 1246 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c drm_get_format_name(mode_cmd->pixel_format, &format_name)); mode_cmd 1257 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c drm_helper_mode_fill_fb_struct(dev, &vfbd->base.base, mode_cmd); mode_cmd 1260 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c vfbd->base.user_handle = mode_cmd->handles[0]; mode_cmd 1313 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c const struct drm_mode_fb_cmd2 *mode_cmd) mode_cmd 1324 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c if (vmw_kms_srf_ok(dev_priv, mode_cmd->width, mode_cmd->height) && mode_cmd 1326 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c mode_cmd->width > 64 && /* Don't create a proxy for cursor */ mode_cmd 1328 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c ret = vmw_create_bo_proxy(dev_priv->dev, mode_cmd, mode_cmd 1339 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c mode_cmd, mode_cmd 1350 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c mode_cmd); mode_cmd 1370 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c const struct drm_mode_fb_cmd2 *mode_cmd) mode_cmd 1389 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c user_obj = ttm_base_object_lookup(tfile, mode_cmd->handles[0]); mode_cmd 1401 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c mode_cmd->handles[0], mode_cmd 1408 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c !vmw_kms_srf_ok(dev_priv, mode_cmd->width, mode_cmd->height)) { mode_cmd 1418 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c mode_cmd); mode_cmd 441 drivers/gpu/drm/vmwgfx/vmwgfx_kms.h const struct drm_mode_fb_cmd2 *mode_cmd); mode_cmd 55 drivers/gpu/drm/xen/xen_drm_front_kms.c const struct drm_mode_fb_cmd2 *mode_cmd) mode_cmd 62 drivers/gpu/drm/xen/xen_drm_front_kms.c fb = drm_gem_fb_create_with_funcs(dev, filp, mode_cmd, &fb_funcs); mode_cmd 66 drivers/gpu/drm/xen/xen_drm_front_kms.c gem_obj = drm_gem_object_lookup(filp, mode_cmd->handles[0]); mode_cmd 311 include/drm/drm_fourcc.h const struct drm_mode_fb_cmd2 *mode_cmd); mode_cmd 23 include/drm/drm_gem_framebuffer_helper.h const struct drm_mode_fb_cmd2 *mode_cmd, mode_cmd 27 include/drm/drm_gem_framebuffer_helper.h const struct drm_mode_fb_cmd2 *mode_cmd); mode_cmd 30 include/drm/drm_gem_framebuffer_helper.h const struct drm_mode_fb_cmd2 *mode_cmd); mode_cmd 79 include/drm/drm_mode_config.h const struct drm_mode_fb_cmd2 *mode_cmd); mode_cmd 92 include/drm/drm_mode_config.h const struct drm_format_info *(*get_format_info)(const struct drm_mode_fb_cmd2 *mode_cmd); mode_cmd 36 include/drm/drm_modeset_helper.h const struct drm_mode_fb_cmd2 *mode_cmd);