mode_clock        104 drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c 	unsigned mode_clock, max_tmds_clock;
mode_clock        167 drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c 			mode_clock = amdgpu_connector->pixelclock_for_modeset;
mode_clock        173 drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c 				  connector->name, mode_clock, max_tmds_clock);
mode_clock        176 drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c 			if ((bpc == 12) && (mode_clock * 3/2 > max_tmds_clock)) {
mode_clock        178 drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c 				    (mode_clock * 5/4 <= max_tmds_clock))
mode_clock        187 drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c 			if ((bpc == 10) && (mode_clock * 5/4 > max_tmds_clock)) {
mode_clock        119 drivers/gpu/drm/arc/arcpgu_drv.c 	unsigned long mode_clock = arcpgu->crtc.mode.crtc_clock * 1000;
mode_clock        122 drivers/gpu/drm/arc/arcpgu_drv.c 	seq_printf(m, "mode: %lu\n", mode_clock);
mode_clock        215 drivers/gpu/drm/arm/hdlcd_drv.c 	unsigned long mode_clock = hdlcd->crtc.mode.crtc_clock * 1000;
mode_clock        218 drivers/gpu/drm/arm/hdlcd_drv.c 	seq_printf(m, "mode: %lu\n", mode_clock);
mode_clock        497 drivers/gpu/drm/i915/display/intel_dp.c u32 intel_dp_mode_to_fec_clock(u32 mode_clock)
mode_clock        499 drivers/gpu/drm/i915/display/intel_dp.c 	return div_u64(mul_u32_u32(mode_clock, 1000000U),
mode_clock        504 drivers/gpu/drm/i915/display/intel_dp.c 				       u32 mode_clock, u32 mode_hdisplay)
mode_clock        516 drivers/gpu/drm/i915/display/intel_dp.c 			 intel_dp_mode_to_fec_clock(mode_clock);
mode_clock        551 drivers/gpu/drm/i915/display/intel_dp.c 				       int mode_clock, int mode_hdisplay)
mode_clock        556 drivers/gpu/drm/i915/display/intel_dp.c 	if (mode_clock <= DP_DSC_PEAK_PIXEL_RATE)
mode_clock        557 drivers/gpu/drm/i915/display/intel_dp.c 		min_slice_count = DIV_ROUND_UP(mode_clock,
mode_clock        560 drivers/gpu/drm/i915/display/intel_dp.c 		min_slice_count = DIV_ROUND_UP(mode_clock,
mode_clock        117 drivers/gpu/drm/i915/display/intel_dp.h u32 intel_dp_mode_to_fec_clock(u32 mode_clock);
mode_clock        832 drivers/gpu/drm/i915/display/intel_sdvo.c 	int mode_clock;
mode_clock        849 drivers/gpu/drm/i915/display/intel_sdvo.c 	mode_clock = mode->clock;
mode_clock        850 drivers/gpu/drm/i915/display/intel_sdvo.c 	mode_clock /= 10;
mode_clock        851 drivers/gpu/drm/i915/display/intel_sdvo.c 	dtd->part1.clock = mode_clock;
mode_clock        127 drivers/gpu/drm/radeon/radeon_connectors.c 	int mode_clock, max_tmds_clock;
mode_clock        197 drivers/gpu/drm/radeon/radeon_connectors.c 			mode_clock = radeon_connector->pixelclock_for_modeset;
mode_clock        203 drivers/gpu/drm/radeon/radeon_connectors.c 					  connector->name, mode_clock, max_tmds_clock);
mode_clock        206 drivers/gpu/drm/radeon/radeon_connectors.c 			if ((bpc == 12) && (mode_clock * 3/2 > max_tmds_clock)) {
mode_clock        208 drivers/gpu/drm/radeon/radeon_connectors.c 					(mode_clock * 5/4 <= max_tmds_clock))
mode_clock        217 drivers/gpu/drm/radeon/radeon_connectors.c 			if ((bpc == 10) && (mode_clock * 5/4 > max_tmds_clock)) {
mode_clock        215 drivers/gpu/drm/rcar-du/rcar_du_crtc.c 	unsigned long mode_clock = mode->clock * 1000;
mode_clock        220 drivers/gpu/drm/rcar-du/rcar_du_crtc.c 		unsigned long target = mode_clock;
mode_clock        273 drivers/gpu/drm/rcar-du/rcar_du_crtc.c 		rcar_du_escr_divider(rcrtc->clock, mode_clock,
mode_clock        276 drivers/gpu/drm/rcar-du/rcar_du_crtc.c 			rcar_du_escr_divider(rcrtc->extclock, mode_clock,
mode_clock        280 drivers/gpu/drm/rcar-du/rcar_du_crtc.c 			mode_clock, params.clk == rcrtc->clock ? "cpg" : "ext",