mode0             221 arch/mips/cavium-octeon/executive/cvmx-helper-util.c 				pko_mode.s.mode0 = 4;
mode0             223 arch/mips/cavium-octeon/executive/cvmx-helper-util.c 				pko_mode.s.mode0 = 3;
mode0             225 arch/mips/cavium-octeon/executive/cvmx-helper-util.c 				pko_mode.s.mode0 = 2;
mode0             227 arch/mips/cavium-octeon/executive/cvmx-helper-util.c 				pko_mode.s.mode0 = 1;
mode0             229 arch/mips/cavium-octeon/executive/cvmx-helper-util.c 				pko_mode.s.mode0 = 0;
mode0            1945 arch/mips/include/asm/octeon/cvmx-pko-defs.h 		uint64_t mode0:3;
mode0            1947 arch/mips/include/asm/octeon/cvmx-pko-defs.h 		uint64_t mode0:3;
mode0             227 drivers/block/swim.c 		swim_write(base, mode0, 0xf8);
mode0             310 drivers/block/swim.c 		swim_write(base, mode0, EXTERNAL_DRIVE); /* clear drive 1 bit */
mode0             313 drivers/block/swim.c 		swim_write(base, mode0, INTERNAL_DRIVE); /* clear drive 0 bit */
mode0             469 drivers/block/swim.c 	swim_write(base, mode0, side);
mode0             483 drivers/block/swim.c 	swim_write(base, mode0, MOTON);
mode0            1055 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c 	struct drm_display_mode *mode0 = NULL;
mode0            1070 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c 		mode0 = &adev->mode_info.crtcs[i]->base.mode;
mode0            1072 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c 		lb_size = dce_v6_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i], mode0, mode1);
mode0            1074 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c 		lb_size = dce_v6_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i+1], mode1, mode0);
mode0            2323 drivers/gpu/drm/radeon/evergreen.c 	struct drm_display_mode *mode0 = NULL;
mode0            2338 drivers/gpu/drm/radeon/evergreen.c 		mode0 = &rdev->mode_info.crtcs[i]->base.mode;
mode0            2340 drivers/gpu/drm/radeon/evergreen.c 		lb_size = evergreen_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i], mode0, mode1);
mode0            2342 drivers/gpu/drm/radeon/evergreen.c 		lb_size = evergreen_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i+1], mode1, mode0);
mode0             895 drivers/gpu/drm/radeon/rs600.c 	struct drm_display_mode *mode0 = NULL;
mode0             906 drivers/gpu/drm/radeon/rs600.c 		mode0 = &rdev->mode_info.crtcs[0]->base.mode;
mode0             910 drivers/gpu/drm/radeon/rs600.c 	rs690_line_buffer_adjust(rdev, mode0, mode1);
mode0             463 drivers/gpu/drm/radeon/rs690.c 					struct drm_display_mode *mode0,
mode0             474 drivers/gpu/drm/radeon/rs690.c 	if (mode0 && mode1) {
mode0             527 drivers/gpu/drm/radeon/rs690.c 	} else if (mode0) {
mode0             586 drivers/gpu/drm/radeon/rs690.c 	struct drm_display_mode *mode0 = NULL;
mode0             600 drivers/gpu/drm/radeon/rs690.c 		mode0 = &rdev->mode_info.crtcs[0]->base.mode;
mode0             613 drivers/gpu/drm/radeon/rs690.c 		if (mode0)
mode0             619 drivers/gpu/drm/radeon/rs690.c 	rs690_line_buffer_adjust(rdev, mode0, mode1);
mode0             638 drivers/gpu/drm/radeon/rs690.c 				    mode0, mode1,
mode0             642 drivers/gpu/drm/radeon/rs690.c 				    mode0, mode1,
mode0            1114 drivers/gpu/drm/radeon/rv515.c 					struct drm_display_mode *mode0,
mode0            1125 drivers/gpu/drm/radeon/rv515.c 	if (mode0 && mode1) {
mode0            1178 drivers/gpu/drm/radeon/rv515.c 	} else if (mode0) {
mode0            1237 drivers/gpu/drm/radeon/rv515.c 	struct drm_display_mode *mode0 = NULL;
mode0            1246 drivers/gpu/drm/radeon/rv515.c 		mode0 = &rdev->mode_info.crtcs[0]->base.mode;
mode0            1249 drivers/gpu/drm/radeon/rv515.c 	rs690_line_buffer_adjust(rdev, mode0, mode1);
mode0            1263 drivers/gpu/drm/radeon/rv515.c 				    mode0, mode1,
mode0            1267 drivers/gpu/drm/radeon/rv515.c 				    mode0, mode1,
mode0            1279 drivers/gpu/drm/radeon/rv515.c 	struct drm_display_mode *mode0 = NULL;
mode0            1288 drivers/gpu/drm/radeon/rv515.c 		mode0 = &rdev->mode_info.crtcs[0]->base.mode;
mode0            1303 drivers/gpu/drm/radeon/rv515.c 		if (mode0)
mode0            2466 drivers/gpu/drm/radeon/si.c 	struct drm_display_mode *mode0 = NULL;
mode0            2481 drivers/gpu/drm/radeon/si.c 		mode0 = &rdev->mode_info.crtcs[i]->base.mode;
mode0            2483 drivers/gpu/drm/radeon/si.c 		lb_size = dce6_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i], mode0, mode1);
mode0            2485 drivers/gpu/drm/radeon/si.c 		lb_size = dce6_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i+1], mode1, mode0);
mode0             259 drivers/rtc/rtc-pcf85063.c 	s8 mode0, mode1, reg;
mode0             267 drivers/rtc/rtc-pcf85063.c 	mode0 = DIV_ROUND_CLOSEST(offset, PCF85063_OFFSET_STEP0);
mode0             270 drivers/rtc/rtc-pcf85063.c 	error0 = abs(offset - (mode0 * PCF85063_OFFSET_STEP0));
mode0             273 drivers/rtc/rtc-pcf85063.c 		reg = mode0 & ~PCF85063_OFFSET_MODE;