mmusr 184 arch/m68k/kernel/traps.c unsigned long mmusr; mmusr 194 arch/m68k/kernel/traps.c asm volatile (".chip 68040; movec %%mmusr,%0; .chip 68k" : "=r" (mmusr)); mmusr 198 arch/m68k/kernel/traps.c return mmusr; mmusr 299 arch/m68k/kernel/traps.c unsigned long mmusr; mmusr 320 arch/m68k/kernel/traps.c mmusr = probe040(!(ssw & RW_040), addr, ssw); mmusr 321 arch/m68k/kernel/traps.c pr_debug("mmusr = %lx\n", mmusr); mmusr 323 arch/m68k/kernel/traps.c if (!(mmusr & MMU_R_040)) { mmusr 504 arch/m68k/kernel/traps.c unsigned short mmusr; mmusr 547 arch/m68k/kernel/traps.c mmusr = temp; mmusr 548 arch/m68k/kernel/traps.c errorcode = (mmusr & MMU_I) ? 0 : 1; mmusr 552 arch/m68k/kernel/traps.c if (mmusr & (MMU_I | MMU_WP)) { mmusr 564 arch/m68k/kernel/traps.c } else if (!(mmusr & MMU_I)) { mmusr 568 arch/m68k/kernel/traps.c mmusr); mmusr 569 arch/m68k/kernel/traps.c } else if (mmusr & (MMU_B|MMU_L|MMU_S)) { mmusr 573 arch/m68k/kernel/traps.c die_if_kernel("Oops",&fp->ptregs,mmusr); mmusr 588 arch/m68k/kernel/traps.c mmusr = temp; mmusr 590 arch/m68k/kernel/traps.c pr_err("level 0 mmusr is %#x\n", mmusr); mmusr 600 arch/m68k/kernel/traps.c die_if_kernel("Oops",&fp->ptregs,mmusr); mmusr 655 arch/m68k/kernel/traps.c mmusr = temp; mmusr 656 arch/m68k/kernel/traps.c if (mmusr & MMU_I) mmusr 658 arch/m68k/kernel/traps.c else if (mmusr & (MMU_B|MMU_L|MMU_S)) { mmusr 662 arch/m68k/kernel/traps.c die_if_kernel("Oops",&fp->ptregs,mmusr); mmusr 704 arch/m68k/kernel/traps.c unsigned long mmusr, addr; mmusr 708 arch/m68k/kernel/traps.c mmusr = mmu_read(MMUSR); mmusr 750 arch/m68k/kernel/traps.c if ((fs == 13) && (mmusr & MMUSR_WF)) /* rd-mod-wr access */ mmusr 40 arch/m68k/mm/cache.c unsigned long mmusr; mmusr 46 arch/m68k/mm/cache.c : "=r" (mmusr) mmusr 49 arch/m68k/mm/cache.c if (mmusr & MMU_R_040) mmusr 50 arch/m68k/mm/cache.c return (mmusr & PAGE_MASK) | (vaddr & ~PAGE_MASK); mmusr 52 arch/m68k/mm/cache.c unsigned short mmusr; mmusr 57 arch/m68k/mm/cache.c : "=a&" (descaddr), "=m" (mmusr) mmusr 59 arch/m68k/mm/cache.c if (mmusr & (MMU_I|MMU_B|MMU_L)) mmusr 62 arch/m68k/mm/cache.c switch (mmusr & MMU_NUM) {