mmr_base 90 arch/ia64/uv/kernel/setup.c unsigned long mmr_base, lowmem_redir_base, lowmem_redir_size; mmr_base 95 arch/ia64/uv/kernel/setup.c mmr_base = uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR) & mmr_base 100 arch/ia64/uv/kernel/setup.c printk(KERN_DEBUG "UV: global MMR base 0x%lx\n", mmr_base); mmr_base 115 arch/ia64/uv/kernel/setup.c uv_cpu_hub_info(cpu)->global_mmr_base = mmr_base; mmr_base 44 arch/x86/include/asm/uv/bios.h u64 mmr_base; mmr_base 1163 arch/x86/kernel/apic/x2apic_uv_x.c hi->global_mmr_base = uv_gp_table->mmr_base; mmr_base 1191 arch/x86/kernel/apic/x2apic_uv_x.c uv_gp_table->mmr_base, uv_gp_table->mmr_shift, mmr_base 1349 drivers/dma/iop-adma.c iop_chan->mmr_base = devm_ioremap(&pdev->dev, res->start, mmr_base 1351 drivers/dma/iop-adma.c if (!iop_chan->mmr_base) { mmr_base 12 drivers/dma/iop-adma.h #define DMA_CCR(chan) (chan->mmr_base + 0x0) mmr_base 13 drivers/dma/iop-adma.h #define DMA_CSR(chan) (chan->mmr_base + 0x4) mmr_base 14 drivers/dma/iop-adma.h #define DMA_DAR(chan) (chan->mmr_base + 0xc) mmr_base 15 drivers/dma/iop-adma.h #define DMA_NDAR(chan) (chan->mmr_base + 0x10) mmr_base 16 drivers/dma/iop-adma.h #define DMA_PADR(chan) (chan->mmr_base + 0x14) mmr_base 17 drivers/dma/iop-adma.h #define DMA_PUADR(chan) (chan->mmr_base + 0x18) mmr_base 18 drivers/dma/iop-adma.h #define DMA_LADR(chan) (chan->mmr_base + 0x1c) mmr_base 19 drivers/dma/iop-adma.h #define DMA_BCR(chan) (chan->mmr_base + 0x20) mmr_base 20 drivers/dma/iop-adma.h #define DMA_DCR(chan) (chan->mmr_base + 0x24) mmr_base 23 drivers/dma/iop-adma.h #define AAU_ACR(chan) (chan->mmr_base + 0x0) mmr_base 24 drivers/dma/iop-adma.h #define AAU_ASR(chan) (chan->mmr_base + 0x4) mmr_base 25 drivers/dma/iop-adma.h #define AAU_ADAR(chan) (chan->mmr_base + 0x8) mmr_base 26 drivers/dma/iop-adma.h #define AAU_ANDAR(chan) (chan->mmr_base + 0xc) mmr_base 27 drivers/dma/iop-adma.h #define AAU_SAR(src, chan) (chan->mmr_base + (0x10 + ((src) << 2))) mmr_base 28 drivers/dma/iop-adma.h #define AAU_DAR(chan) (chan->mmr_base + 0x20) mmr_base 29 drivers/dma/iop-adma.h #define AAU_ABCR(chan) (chan->mmr_base + 0x24) mmr_base 30 drivers/dma/iop-adma.h #define AAU_ADCR(chan) (chan->mmr_base + 0x28) mmr_base 31 drivers/dma/iop-adma.h #define AAU_SAR_EDCR(src_edc) (chan->mmr_base + (0x02c + ((src_edc-4) << 2))) mmr_base 1098 drivers/dma/mv_xor.c mv_chan->mmr_base = xordev->xor_base; mmr_base 44 drivers/dma/mv_xor.h #define XOR_CONFIG(chan) (chan->mmr_base + 0x10 + (chan->idx * 4)) mmr_base 45 drivers/dma/mv_xor.h #define XOR_ACTIVATION(chan) (chan->mmr_base + 0x20 + (chan->idx * 4)) mmr_base 46 drivers/dma/mv_xor.h #define XOR_INTR_CAUSE(chan) (chan->mmr_base + 0x30) mmr_base 47 drivers/dma/mv_xor.h #define XOR_INTR_MASK(chan) (chan->mmr_base + 0x40) mmr_base 48 drivers/dma/mv_xor.h #define XOR_ERROR_CAUSE(chan) (chan->mmr_base + 0x50) mmr_base 49 drivers/dma/mv_xor.h #define XOR_ERROR_ADDR(chan) (chan->mmr_base + 0x60) mmr_base 107 drivers/dma/mv_xor.h void __iomem *mmr_base; mmr_base 56 include/linux/platform_data/dma-iop32x.h void __iomem *mmr_base;