mmioaddr 678 arch/mips/txx9/generic/setup.c void __iomem *mmioaddr; mmioaddr 700 arch/mips/txx9/generic/setup.c writeb(data->cur_val, data->mmioaddr); mmioaddr 736 arch/mips/txx9/generic/setup.c iocled->mmioaddr = ioremap(baseaddr, 1); mmioaddr 737 arch/mips/txx9/generic/setup.c if (!iocled->mmioaddr) mmioaddr 776 arch/mips/txx9/generic/setup.c iounmap(iocled->mmioaddr); mmioaddr 331 drivers/gpu/drm/i915/i915_drv.h i915_reg_t mmioaddr[20]; mmioaddr 186 drivers/gpu/drm/i915/intel_csr.c u32 mmioaddr[DMC_V1_MAX_MMIO_COUNT]; mmioaddr 212 drivers/gpu/drm/i915/intel_csr.c u32 mmioaddr[DMC_V3_MAX_MMIO_COUNT]; mmioaddr 321 drivers/gpu/drm/i915/intel_csr.c I915_WRITE(dev_priv->csr.mmioaddr[i], mmioaddr 379 drivers/gpu/drm/i915/intel_csr.c const u32 *mmioaddr, *mmiodata; mmioaddr 383 drivers/gpu/drm/i915/intel_csr.c BUILD_BUG_ON(ARRAY_SIZE(csr->mmioaddr) < DMC_V3_MAX_MMIO_COUNT || mmioaddr 384 drivers/gpu/drm/i915/intel_csr.c ARRAY_SIZE(csr->mmioaddr) < DMC_V1_MAX_MMIO_COUNT); mmioaddr 401 drivers/gpu/drm/i915/intel_csr.c mmioaddr = v3->mmioaddr; mmioaddr 415 drivers/gpu/drm/i915/intel_csr.c mmioaddr = v1->mmioaddr; mmioaddr 440 drivers/gpu/drm/i915/intel_csr.c if (mmioaddr[i] < CSR_MMIO_START_RANGE || mmioaddr 441 drivers/gpu/drm/i915/intel_csr.c mmioaddr[i] > CSR_MMIO_END_RANGE) { mmioaddr 443 drivers/gpu/drm/i915/intel_csr.c mmioaddr[i]); mmioaddr 446 drivers/gpu/drm/i915/intel_csr.c csr->mmioaddr[i] = _MMIO(mmioaddr[i]);