mmcra              30 arch/powerpc/include/asm/oprofile_impl.h 	unsigned long mmcra;
mmcra             487 arch/powerpc/kernel/sysfs.c SYSFS_PMCSETUP(mmcra, SPRN_MMCRA);
mmcra             498 arch/powerpc/kernel/sysfs.c static DEVICE_ATTR(mmcra, 0600, show_mmcra, store_mmcra);
mmcra             129 arch/powerpc/oprofile/common.c 	oprofilefs_create_ulong(root, "mmcra", &sys.mmcra);
mmcra             105 arch/powerpc/oprofile/op_model_power4.c 	mmcra_val = sys->mmcra;
mmcra             172 arch/powerpc/oprofile/op_model_power4.c 	unsigned long mmcra = mmcra_val;
mmcra             187 arch/powerpc/oprofile/op_model_power4.c 		mmcra |= MMCRA_SAMPLE_ENABLE;
mmcra             188 arch/powerpc/oprofile/op_model_power4.c 	mtspr(SPRN_MMCRA, mmcra);
mmcra             280 arch/powerpc/oprofile/op_model_power4.c 	unsigned long mmcra;
mmcra             287 arch/powerpc/oprofile/op_model_power4.c 	mmcra = mfspr(SPRN_MMCRA);
mmcra             289 arch/powerpc/oprofile/op_model_power4.c 	if (use_slot_nums && (mmcra & MMCRA_SAMPLE_ENABLE)) {
mmcra             290 arch/powerpc/oprofile/op_model_power4.c 		slot = ((mmcra & MMCRA_SLOT) >> MMCRA_SLOT_SHIFT);
mmcra             297 arch/powerpc/oprofile/op_model_power4.c 	    (mmcra & cur_cpu_spec->oprofile_mmcra_sihv))
mmcra             302 arch/powerpc/oprofile/op_model_power4.c 	if (mmcra & cur_cpu_spec->oprofile_mmcra_sipr)
mmcra             324 arch/powerpc/oprofile/op_model_power4.c static int get_kernel(unsigned long pc, unsigned long mmcra)
mmcra             331 arch/powerpc/oprofile/op_model_power4.c 		is_kernel = ((mmcra & cur_cpu_spec->oprofile_mmcra_sipr) == 0);
mmcra             367 arch/powerpc/oprofile/op_model_power4.c 	unsigned long mmcra;
mmcra             370 arch/powerpc/oprofile/op_model_power4.c 	mmcra = mfspr(SPRN_MMCRA);
mmcra             373 arch/powerpc/oprofile/op_model_power4.c 	is_kernel = get_kernel(pc, mmcra);
mmcra             379 arch/powerpc/oprofile/op_model_power4.c 	if ((mmcra & MMCRA_SIAR_VALID_MASK) == MMCRA_SIAR_VALID_MASK)
mmcra             420 arch/powerpc/oprofile/op_model_power4.c 	mmcra &= ~cur_cpu_spec->oprofile_mmcra_clear;
mmcra             421 arch/powerpc/oprofile/op_model_power4.c 	mtspr(SPRN_MMCRA, mmcra);
mmcra             163 arch/powerpc/perf/core-book3s.c 	unsigned long mmcra = regs->dsisr;
mmcra             165 arch/powerpc/perf/core-book3s.c 	if ((ppmu->flags & PPMU_HAS_SSLOT) && (mmcra & MMCRA_SAMPLE_ENABLE)) {
mmcra             166 arch/powerpc/perf/core-book3s.c 		unsigned long slot = (mmcra & MMCRA_SLOT) >> MMCRA_SLOT_SHIFT;
mmcra             184 arch/powerpc/perf/core-book3s.c 	unsigned long mmcra = regs->dsisr;
mmcra             201 arch/powerpc/perf/core-book3s.c 		sdar_valid = mmcra & sdsync;
mmcra             204 arch/powerpc/perf/core-book3s.c 	if (!(mmcra & MMCRA_SAMPLE_ENABLE) || sdar_valid)
mmcra             286 arch/powerpc/perf/core-book3s.c 	unsigned long mmcra = mfspr(SPRN_MMCRA);
mmcra             287 arch/powerpc/perf/core-book3s.c 	int marked = mmcra & MMCRA_SAMPLE_ENABLE;
mmcra             290 arch/powerpc/perf/core-book3s.c 	regs->dsisr = mmcra;
mmcra             346 arch/powerpc/perf/core-book3s.c 	unsigned long mmcra = regs->dsisr;
mmcra             347 arch/powerpc/perf/core-book3s.c 	int marked = mmcra & MMCRA_SAMPLE_ENABLE;
mmcra             354 arch/powerpc/perf/core-book3s.c 			return mmcra & POWER7P_MMCRA_SIAR_VALID;
mmcra              72 arch/powerpc/perf/isa207-common.c static void mmcra_sdar_mode(u64 event, unsigned long *mmcra)
mmcra              91 arch/powerpc/perf/isa207-common.c 		if (is_event_marked(event) || (*mmcra & MMCRA_SAMPLE_ENABLE))
mmcra              92 arch/powerpc/perf/isa207-common.c 			*mmcra &= MMCRA_SDAR_MODE_NO_UPDATES;
mmcra              94 arch/powerpc/perf/isa207-common.c 			*mmcra |=  p9_SDAR_MODE(event) << MMCRA_SDAR_MODE_SHIFT;
mmcra              96 arch/powerpc/perf/isa207-common.c 			*mmcra |= MMCRA_SDAR_MODE_DCACHE;
mmcra              98 arch/powerpc/perf/isa207-common.c 		*mmcra |= MMCRA_SDAR_MODE_TLB;
mmcra             230 arch/powerpc/perf/isa207-common.c 	u64 mmcra = mfspr(SPRN_MMCRA);
mmcra             231 arch/powerpc/perf/isa207-common.c 	u64 exp = MMCRA_THR_CTR_EXP(mmcra);
mmcra             232 arch/powerpc/perf/isa207-common.c 	u64 mantissa = MMCRA_THR_CTR_MANT(mmcra);
mmcra             369 arch/powerpc/perf/isa207-common.c 	unsigned long mmcra, mmcr1, mmcr2, unit, combine, psel, cache, val;
mmcra             382 arch/powerpc/perf/isa207-common.c 	mmcra = mmcr1 = mmcr2 = 0;
mmcra             407 arch/powerpc/perf/isa207-common.c 		mmcra_sdar_mode(event[i], &mmcra);
mmcra             420 arch/powerpc/perf/isa207-common.c 			mmcra |= MMCRA_SAMPLE_ENABLE;
mmcra             424 arch/powerpc/perf/isa207-common.c 				mmcra |= (val &  3) << MMCRA_SAMP_MODE_SHIFT;
mmcra             425 arch/powerpc/perf/isa207-common.c 				mmcra |= (val >> 2) << MMCRA_SAMP_ELIG_SHIFT;
mmcra             438 arch/powerpc/perf/isa207-common.c 			mmcra |= val << MMCRA_THR_CTL_SHIFT;
mmcra             440 arch/powerpc/perf/isa207-common.c 			mmcra |= val << MMCRA_THR_SEL_SHIFT;
mmcra             442 arch/powerpc/perf/isa207-common.c 			mmcra |= thresh_cmp_val(val);
mmcra             447 arch/powerpc/perf/isa207-common.c 			mmcra |= val << MMCRA_IFM_SHIFT;
mmcra             481 arch/powerpc/perf/isa207-common.c 	mmcr[2] = mmcra;
mmcra             454 arch/powerpc/perf/power5+-pmu.c 	unsigned long mmcra = 0;
mmcra             579 arch/powerpc/perf/power5+-pmu.c 			mmcra |= MMCRA_SAMPLE_ENABLE;
mmcra             595 arch/powerpc/perf/power5+-pmu.c 	mmcr[2] = mmcra;
mmcra             385 arch/powerpc/perf/power5-pmu.c 	unsigned long mmcra = MMCRA_SDAR_DCACHE_MISS | MMCRA_SDAR_ERAT_MISS;
mmcra             524 arch/powerpc/perf/power5-pmu.c 			mmcra |= MMCRA_SAMPLE_ENABLE;
mmcra             537 arch/powerpc/perf/power5-pmu.c 	mmcr[2] = mmcra;
mmcra             177 arch/powerpc/perf/power6-pmu.c 	unsigned long mmcra = MMCRA_SDAR_DCACHE_MISS | MMCRA_SDAR_ERAT_MISS;
mmcra             242 arch/powerpc/perf/power6-pmu.c 			mmcra |= MMCRA_SAMPLE_ENABLE;
mmcra             252 arch/powerpc/perf/power6-pmu.c 	mmcr[2] = mmcra;
mmcra             248 arch/powerpc/perf/power7-pmu.c 	unsigned long mmcra = MMCRA_SDAR_DCACHE_MISS | MMCRA_SDAR_ERAT_MISS;
mmcra             296 arch/powerpc/perf/power7-pmu.c 			mmcra |= MMCRA_SAMPLE_ENABLE;
mmcra             307 arch/powerpc/perf/power7-pmu.c 	mmcr[2] = mmcra;
mmcra             258 arch/powerpc/perf/ppc970-pmu.c 	unsigned long mmcr0 = 0, mmcr1 = 0, mmcra = 0;
mmcra             381 arch/powerpc/perf/ppc970-pmu.c 			mmcra |= MMCRA_SAMPLE_ENABLE;
mmcra             393 arch/powerpc/perf/ppc970-pmu.c 	mmcra |= 0x2000;	/* mark only one IOP per PPC instruction */
mmcra             398 arch/powerpc/perf/ppc970-pmu.c 	mmcr[2] = mmcra;
mmcra             593 arch/powerpc/platforms/powernv/idle.c 	u64 mmcra;
mmcra             670 arch/powerpc/platforms/powernv/idle.c 		sprs.mmcra	= mfspr(SPRN_MMCRA);
mmcra             703 arch/powerpc/platforms/powernv/idle.c 		unsigned long mmcra;
mmcra             728 arch/powerpc/platforms/powernv/idle.c 		mmcra = mfspr(SPRN_MMCRA);
mmcra             729 arch/powerpc/platforms/powernv/idle.c 		mmcra |= PPC_BIT(60);
mmcra             730 arch/powerpc/platforms/powernv/idle.c 		mtspr(SPRN_MMCRA, mmcra);
mmcra             731 arch/powerpc/platforms/powernv/idle.c 		mmcra &= ~PPC_BIT(60);
mmcra             732 arch/powerpc/platforms/powernv/idle.c 		mtspr(SPRN_MMCRA, mmcra);
mmcra             789 arch/powerpc/platforms/powernv/idle.c 	mtspr(SPRN_MMCRA,	sprs.mmcra);
mmcra              57 tools/perf/arch/powerpc/util/perf_regs.c 	SMPL_REG(mmcra, PERF_REG_POWERPC_MMCRA),