Mode 441 drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h unsigned int Mode; Mode 559 drivers/media/pci/ngene/ngene-core.c com.cmd.StreamControl.Mode = mode; Mode 565 drivers/media/pci/ngene/ngene-core.c com.cmd.StreamControl.Mode); Mode 567 drivers/media/pci/ngene/ngene-core.c chan->Mode = mode; Mode 336 drivers/media/pci/ngene/ngene.h u8 Mode; /* Controls clock source */ Mode 562 drivers/media/pci/ngene/ngene.h u8 Mode; Mode 666 drivers/media/pci/ngene/ngene.h u8 Mode; Mode 1174 drivers/media/tuners/mt2063.c enum mt2063_delivery_sys Mode) Mode 1182 drivers/media/tuners/mt2063.c if (Mode >= MT2063_NUM_RCVR_MODES) Mode 1189 drivers/media/tuners/mt2063.c reg[MT2063_REG_PD1_TGT] & ~0x40) | (RFAGCEN[Mode] Mode 1199 drivers/media/tuners/mt2063.c (LNARIN[Mode] & 0x03); Mode 1209 drivers/media/tuners/mt2063.c (FIFFQEN[Mode] << 7) | (FIFFQ[Mode] << 4); Mode 1233 drivers/media/tuners/mt2063.c (ACLNAMAX[Mode] & 0x1F); Mode 1241 drivers/media/tuners/mt2063.c (LNATGT[Mode] & 0x3F); Mode 1249 drivers/media/tuners/mt2063.c (ACRFMAX[Mode] & 0x1F); Mode 1257 drivers/media/tuners/mt2063.c (PD1TGT[Mode] & 0x3F); Mode 1264 drivers/media/tuners/mt2063.c u8 val = ACFIFMAX[Mode]; Mode 1276 drivers/media/tuners/mt2063.c (PD2TGT[Mode] & 0x3F); Mode 1284 drivers/media/tuners/mt2063.c (RFOVDIS[Mode] ? 0x80 : 0x00); Mode 1292 drivers/media/tuners/mt2063.c (FIFOVDIS[Mode] ? 0x80 : 0x00); Mode 1298 drivers/media/tuners/mt2063.c state->rcvr_mode = Mode; Mode 243 drivers/media/tuners/mxl5005s.c u8 Mode; /* 0: Analog Mode ; 1: Digital Mode */ Mode 1672 drivers/media/tuners/mxl5005s.c u8 Mode, /* 0: Analog Mode ; 1: Digital Mode */ Mode 1696 drivers/media/tuners/mxl5005s.c state->Mode = Mode; Mode 1723 drivers/media/tuners/mxl5005s.c if (state->Mode == 1) /* Digital Mode */ Mode 1737 drivers/media/tuners/mxl5005s.c if (state->Mode == 1) /* Digital Mode */ { Mode 1774 drivers/media/tuners/mxl5005s.c status += MXL_ControlWrite(fe, DN_IQTN_AMP_CUT, state->Mode ? 1 : 0); Mode 1777 drivers/media/tuners/mxl5005s.c status += MXL_ControlWrite(fe, BB_MODE, state->Mode ? 0 : 1); Mode 1778 drivers/media/tuners/mxl5005s.c status += MXL_ControlWrite(fe, BB_BUF, state->Mode ? 3 : 2); Mode 1779 drivers/media/tuners/mxl5005s.c status += MXL_ControlWrite(fe, BB_BUF_OA, state->Mode ? 1 : 0); Mode 1780 drivers/media/tuners/mxl5005s.c status += MXL_ControlWrite(fe, BB_IQSWAP, state->Mode ? 0 : 1); Mode 1784 drivers/media/tuners/mxl5005s.c if (state->Mode) { /* Digital Mode */ Mode 1815 drivers/media/tuners/mxl5005s.c status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, state->Mode ? 5 : 8); Mode 1817 drivers/media/tuners/mxl5005s.c RFSYN_EN_CHP_HIGAIN, state->Mode ? 1 : 1); Mode 1818 drivers/media/tuners/mxl5005s.c status += MXL_ControlWrite(fe, EN_CHP_LIN_B, state->Mode ? 0 : 0); Mode 1825 drivers/media/tuners/mxl5005s.c status += MXL_ControlWrite(fe, AGC_RF, state->Mode ? 15 : 12); Mode 1888 drivers/media/tuners/mxl5005s.c if (state->Mode) { /* Digital Mode */ Mode 1951 drivers/media/tuners/mxl5005s.c if (state->Mode == 0 && state->IF_Mode == 1) /* Analog LowIF mode */ Mode 2034 drivers/media/tuners/mxl5005s.c state->Mode = MXL_DIGITAL_MODE; Mode 2119 drivers/media/tuners/mxl5005s.c if (state->Mode == 0 && state->IF_Mode == 1) /* Analog Low IF mode */ { Mode 2162 drivers/media/tuners/mxl5005s.c if (state->Mode || (state->Mode == 0 && state->IF_Mode == 0)) { Mode 3692 drivers/media/tuners/mxl5005s.c if (state->Mode == 0 && state->IF_Mode == 1) { Mode 3700 drivers/media/tuners/mxl5005s.c if (state->Mode == 0 && state->IF_Mode == 0) { Mode 3708 drivers/media/tuners/mxl5005s.c if (state->Mode == 1) /* Digital Mode */ { Mode 3728 drivers/media/tuners/mxl5005s.c if (state->Mode == 0 && state->IF_Mode == 1) { Mode 3736 drivers/media/tuners/mxl5005s.c if (state->Mode == 0 && state->IF_Mode == 0) { Mode 3744 drivers/media/tuners/mxl5005s.c if (state->Mode == 1) /* Digital Mode */ { Mode 3764 drivers/media/tuners/mxl5005s.c if (state->Mode == 0 && state->IF_Mode == 1) { Mode 3772 drivers/media/tuners/mxl5005s.c if (state->Mode == 0 && state->IF_Mode == 0) { Mode 3780 drivers/media/tuners/mxl5005s.c if (state->Mode == 1) /* Digital Mode */ { Mode 3800 drivers/media/tuners/mxl5005s.c if (state->Mode == 0 && state->IF_Mode == 1) { Mode 3808 drivers/media/tuners/mxl5005s.c if (state->Mode == 0 && state->IF_Mode == 0) { Mode 3816 drivers/media/tuners/mxl5005s.c if (state->Mode == 1) /* Digital Mode */ { Mode 261 drivers/net/hippi/rrunner.c if (readl(®s->Mode) & FATAL_ERR) Mode 275 drivers/net/hippi/rrunner.c if (readl(®s->Mode) & FATAL_ERR) Mode 317 drivers/net/hippi/rrunner.c writel(SWAP_DATA | PTR64BIT | PTR_WD_SWAP, ®s->Mode); Mode 319 drivers/net/hippi/rrunner.c writel(SWAP_DATA | PTR64BIT | PTR_WD_NOSWAP, ®s->Mode); Mode 321 drivers/net/hippi/rrunner.c writel(SWAP_DATA | PTR32BIT | PTR_WD_NOSWAP, ®s->Mode); Mode 1395 drivers/net/hippi/rrunner.c if (readl(®s->Mode) & FATAL_ERR) Mode 132 drivers/net/hippi/rrunner.h u32 Mode; Mode 502 drivers/scsi/aic94xx/aic94xx_reg_def.h #define CSEQm_CIO_REG(Mode, Reg) \ Mode 504 drivers/scsi/aic94xx/aic94xx_reg_def.h ((u32) (Mode) * CSEQ_MODE_PAGE_SIZE) + (u32) (Reg)) Mode 552 drivers/scsi/aic94xx/aic94xx_reg_def.h #define CMnSCBPTR(Mode) CSEQm_CIO_REG(Mode, MnSCBPTR) Mode 554 drivers/scsi/aic94xx/aic94xx_reg_def.h #define CMnDDBPTR(Mode) CSEQm_CIO_REG(Mode, MnDDBPTR) Mode 556 drivers/scsi/aic94xx/aic94xx_reg_def.h #define CMnSCRATCHPAGE(Mode) CSEQm_CIO_REG(Mode, MnSCRATCHPAGE) Mode 564 drivers/scsi/aic94xx/aic94xx_reg_def.h #define CMnREQMBX(Mode) CSEQm_CIO_REG(Mode, 0x30) Mode 571 drivers/scsi/aic94xx/aic94xx_reg_def.h #define CMnRSPMBX(Mode) CSEQm_CIO_REG(Mode, 0x34) Mode 593 drivers/scsi/aic94xx/aic94xx_reg_def.h #define CMnINT(Mode) CSEQm_CIO_REG(Mode, 0x38) Mode 604 drivers/scsi/aic94xx/aic94xx_reg_def.h #define CMnINTEN(Mode) CSEQm_CIO_REG(Mode, 0x3C) Mode 663 drivers/scsi/aic94xx/aic94xx_reg_def.h #define CMnSCRATCH(Mode) CSEQm_CIO_REG(Mode, 0x1E0) Mode 832 drivers/scsi/aic94xx/aic94xx_reg_def.h #define LmSEQ_PHY_BASE(Mode, LinkNum) \ Mode 836 drivers/scsi/aic94xx/aic94xx_reg_def.h ((u32) (Mode) * LmSEQ_MODE_PAGE_SIZE)) Mode 838 drivers/scsi/aic94xx/aic94xx_reg_def.h #define LmSEQ_PHY_REG(Mode, LinkNum, Reg) \ Mode 839 drivers/scsi/aic94xx/aic94xx_reg_def.h (LmSEQ_PHY_BASE(Mode, LinkNum) + (u32) (Reg)) Mode 887 drivers/scsi/aic94xx/aic94xx_reg_def.h #define LmMnSCRATCHPAGE(LinkNum, Mode) LmSEQ_PHY_REG(Mode, LinkNum, \ Mode 896 drivers/scsi/aic94xx/aic94xx_reg_def.h #define LmMnINT(LinkNum, Mode) LmSEQ_PHY_REG(Mode, LinkNum, 0x38) Mode 926 drivers/scsi/aic94xx/aic94xx_reg_def.h #define LmMnINTEN(LinkNum, Mode) LmSEQ_PHY_REG(Mode, LinkNum, 0x3C) Mode 986 drivers/scsi/aic94xx/aic94xx_reg_def.h #define LmMnDMAERRS(LinkNum, Mode) LmSEQ_PHY_REG(Mode, LinkNum, 0x46) Mode 988 drivers/scsi/aic94xx/aic94xx_reg_def.h #define LmMnSGDMAERRS(LinkNum, Mode) LmSEQ_PHY_REG(Mode, LinkNum, 0x47) Mode 1019 drivers/scsi/aic94xx/aic94xx_reg_def.h #define LmMnBUFSTAT(LinkNum, Mode) LmSEQ_PHY_REG(Mode, LinkNum, 0x4E) Mode 1024 drivers/scsi/aic94xx/aic94xx_reg_def.h #define LmMnXFRLVL(LinkNum, Mode) LmSEQ_PHY_REG(Mode, LinkNum, 0x59) Mode 1034 drivers/scsi/aic94xx/aic94xx_reg_def.h #define LmMnSGDMACTL(LinkNum, Mode) LmSEQ_PHY_REG(Mode, LinkNum, 0x5A) Mode 1041 drivers/scsi/aic94xx/aic94xx_reg_def.h #define LmMnSGDMASTAT(LinkNum, Mode) LmSEQ_PHY_REG(Mode, LinkNum, 0x5B) Mode 1044 drivers/scsi/aic94xx/aic94xx_reg_def.h #define LmMnDDMACTL(LinkNum, Mode) LmSEQ_PHY_REG(Mode, LinkNum, 0x5C) Mode 1055 drivers/scsi/aic94xx/aic94xx_reg_def.h #define LmMnDDMASTAT(LinkNum, Mode) LmSEQ_PHY_REG(Mode, LinkNum, 0x5D) Mode 1067 drivers/scsi/aic94xx/aic94xx_reg_def.h #define LmMnDDMAMODE(LinkNum, Mode) LmSEQ_PHY_REG(Mode, LinkNum, 0x5E) Mode 1086 drivers/scsi/aic94xx/aic94xx_reg_def.h #define LmMnXFRCNT(LinkNum, Mode) LmSEQ_PHY_REG(Mode, LinkNum, 0x70) Mode 1089 drivers/scsi/aic94xx/aic94xx_reg_def.h #define LmMnDPSEL(LinkNum, Mode) LmSEQ_PHY_REG(Mode, LinkNum, 0x7B) Mode 1113 drivers/scsi/aic94xx/aic94xx_reg_def.h #define LmMnDPACC(LinkNum, Mode) LmSEQ_PHY_REG(Mode, LinkNum, 0x78) Mode 1117 drivers/scsi/aic94xx/aic94xx_reg_def.h #define LmMnHOLDLVL(LinkNum, Mode) LmSEQ_PHY_REG(Mode, LinkNum, 0x7D) Mode 1192 drivers/scsi/aic94xx/aic94xx_reg_def.h #define LmMnSATAFS(LinkNum, Mode) LmSEQ_PHY_REG(Mode, LinkNum, 0x7E) Mode 1193 drivers/scsi/aic94xx/aic94xx_reg_def.h #define LmMnXMTSIZE(LinkNum, Mode) LmSEQ_PHY_REG(Mode, LinkNum, 0x93) Mode 1196 drivers/scsi/aic94xx/aic94xx_reg_def.h #define LmMnFRMERR(LinkNum, Mode) LmSEQ_PHY_REG(Mode, LinkNum, 0xB0) Mode 1256 drivers/scsi/aic94xx/aic94xx_reg_def.h #define LmMnDATABUFADR(LinkNum, Mode) LmSEQ_PHY_REG(Mode, LinkNum, 0xC8) Mode 1259 drivers/scsi/aic94xx/aic94xx_reg_def.h #define LmMnDATABUF(LinkNum, Mode) LmSEQ_PHY_REG(Mode, LinkNum, 0xCA) Mode 306 drivers/scsi/hpsa_cmd.h u8 Mode:2; /* b00 */ Mode 311 drivers/scsi/hpsa_cmd.h u8 Mode:2; /* b01 */ Mode 317 drivers/scsi/hpsa_cmd.h u8 Mode:2; /* b10 */ Mode 324 drivers/scsi/hpsa_cmd.h u32 Mode:2; Mode 331 drivers/scsi/hpsa_cmd.h u32 Mode:2; Mode 150 drivers/staging/rtl8188eu/hal/rtl8188e_cmd.c void rtl8188e_set_FwPwrMode_cmd(struct adapter *adapt, u8 Mode) Mode 157 drivers/staging/rtl8188eu/hal/rtl8188e_cmd.c Mode, pwrpriv->smart_ps, adapt->registrypriv.uapsd_enable); Mode 159 drivers/staging/rtl8188eu/hal/rtl8188e_cmd.c switch (Mode) { Mode 161 drivers/staging/rtl8188eu/hal/rtl8188e_cmd.c H2CSetPwrMode.Mode = 0; Mode 164 drivers/staging/rtl8188eu/hal/rtl8188e_cmd.c H2CSetPwrMode.Mode = 1; Mode 168 drivers/staging/rtl8188eu/hal/rtl8188e_cmd.c H2CSetPwrMode.Mode = 1; Mode 172 drivers/staging/rtl8188eu/hal/rtl8188e_cmd.c H2CSetPwrMode.Mode = 1; Mode 175 drivers/staging/rtl8188eu/hal/rtl8188e_cmd.c H2CSetPwrMode.Mode = 2; Mode 178 drivers/staging/rtl8188eu/hal/rtl8188e_cmd.c H2CSetPwrMode.Mode = 0; Mode 188 drivers/staging/rtl8188eu/hal/rtl8188e_cmd.c if (Mode > 0) Mode 49 drivers/staging/rtl8188eu/include/rtl8188e_cmd.h u8 Mode;/* 0:Active,1:LPS,2:WMMPS */ Mode 65 drivers/staging/rtl8188eu/include/rtl8188e_cmd.h void rtl8188e_set_FwPwrMode_cmd(struct adapter *padapter, u8 Mode); Mode 166 drivers/staging/rtl8723bs/include/rtl8723b_cmd.h void rtl8723b_set_FwPwrMode_cmd(struct adapter *padapter, u8 Mode); Mode 975 fs/cifs/cifspdu.h __le16 Mode; Mode 2330 fs/cifs/cifspdu.h __le32 Mode; Mode 2514 fs/cifs/cifspdu.h __le32 Mode; Mode 1328 fs/cifs/cifssmb.c pSMB->Mode = cpu_to_le16(access_flags_to_smbopen_mode(access_flags)); Mode 1329 fs/cifs/cifssmb.c pSMB->Mode |= cpu_to_le16(0x40); /* deny none */ Mode 432 fs/cifs/smb2inode.c dst->Mode = src->Mode; Mode 742 fs/cifs/smb2pdu.c cpu_to_le16(offsetof(struct create_posix, Mode)); Mode 765 fs/cifs/smb2pdu.c buf->Mode = cpu_to_le32(mode); Mode 792 fs/cifs/smb2pdu.h __le32 Mode; Mode 1563 fs/cifs/smb2pdu.h __le32 Mode; Mode 61 include/uapi/linux/cciss_defs.h BYTE Mode:2; /* b00 */ Mode 66 include/uapi/linux/cciss_defs.h BYTE Mode:2; /* b01 */ Mode 72 include/uapi/linux/cciss_defs.h BYTE Mode:2; /* b10 */ Mode 79 include/uapi/linux/cciss_defs.h DWORD Mode:2; Mode 85 include/uapi/linux/cciss_defs.h DWORD Mode:2;