MinVddcPhases      50 drivers/gpu/drm/amd/powerplay/inc/smu71_discrete.h     uint32_t    MinVddcPhases;
MinVddcPhases      80 drivers/gpu/drm/amd/powerplay/inc/smu71_discrete.h     uint32_t    MinVddcPhases;
MinVddcPhases     113 drivers/gpu/drm/amd/powerplay/inc/smu71_discrete.h     uint32_t    MinVddcPhases;
MinVddcPhases     191 drivers/gpu/drm/amd/powerplay/inc/smu71_discrete.h     uint8_t  MinVddcPhases;
MinVddcPhases     107 drivers/gpu/drm/amd/powerplay/inc/smu7_discrete.h     uint32_t    MinVddcPhases;
MinVddcPhases     138 drivers/gpu/drm/amd/powerplay/inc/smu7_discrete.h     uint32_t    MinVddcPhases;
MinVddcPhases     171 drivers/gpu/drm/amd/powerplay/inc/smu7_discrete.h     uint32_t    MinVddcPhases;
MinVddcPhases     245 drivers/gpu/drm/amd/powerplay/inc/smu7_discrete.h     uint8_t  MinVddcPhases;
MinVddcPhases     425 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	level->MinVddcPhases = 1;
MinVddcPhases     431 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 				&level->MinVddcPhases);
MinVddcPhases     456 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 		CONVERT_FROM_HOST_TO_SMC_UL(level->MinVddcPhases);
MinVddcPhases    1210 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	memory_level->MinVddcPhases = 1;
MinVddcPhases    1214 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 				memory_clock, &memory_level->MinVddcPhases);
MinVddcPhases    1277 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 		CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MinVddcPhases);
MinVddcPhases    1397 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	table->ACPILevel.MinVddcPhases = data->vddc_phase_shed_control ? 0 : 1;
MinVddcPhases    1445 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	table->MemoryACPILevel.MinVddcPhases = table->ACPILevel.MinVddcPhases;
MinVddcPhases    1534 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 		table->UvdLevel[count].MinVddcPhases = 1;
MinVddcPhases     909 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	graphic_level->MinVddcPhases = 1;
MinVddcPhases     915 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 				&graphic_level->MinVddcPhases);
MinVddcPhases     945 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 		CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->MinVddcPhases);
MinVddcPhases    1258 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	memory_level->MinVddcPhases = 1;
MinVddcPhases    1262 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 				memory_clock, &memory_level->MinVddcPhases);
MinVddcPhases    1325 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 		CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MinVddcPhases);
MinVddcPhases    1445 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	table->ACPILevel.MinVddcPhases = vddc_phase_shed_control ? 0 : 1;
MinVddcPhases    1493 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	table->MemoryACPILevel.MinVddcPhases = table->ACPILevel.MinVddcPhases;
MinVddcPhases    2665 drivers/gpu/drm/radeon/ci_dpm.c 		table->UvdLevel[count].MinVddcPhases = 1;
MinVddcPhases    2907 drivers/gpu/drm/radeon/ci_dpm.c 	memory_level->MinVddcPhases = 1;
MinVddcPhases    2913 drivers/gpu/drm/radeon/ci_dpm.c 						      &memory_level->MinVddcPhases);
MinVddcPhases    2970 drivers/gpu/drm/radeon/ci_dpm.c 	memory_level->MinVddcPhases = cpu_to_be32(memory_level->MinVddcPhases);
MinVddcPhases    3008 drivers/gpu/drm/radeon/ci_dpm.c 	table->ACPILevel.MinVddcPhases = pi->vddc_phase_shed_control ? 0 : 1;
MinVddcPhases    3038 drivers/gpu/drm/radeon/ci_dpm.c 	table->ACPILevel.MinVddcPhases = cpu_to_be32(table->ACPILevel.MinVddcPhases);
MinVddcPhases    3050 drivers/gpu/drm/radeon/ci_dpm.c 	table->MemoryACPILevel.MinVddcPhases = table->ACPILevel.MinVddcPhases;
MinVddcPhases    3236 drivers/gpu/drm/radeon/ci_dpm.c 	graphic_level->MinVddcPhases = 1;
MinVddcPhases    3242 drivers/gpu/drm/radeon/ci_dpm.c 						      &graphic_level->MinVddcPhases);
MinVddcPhases    3263 drivers/gpu/drm/radeon/ci_dpm.c 	graphic_level->MinVddcPhases = cpu_to_be32(graphic_level->MinVddcPhases);
MinVddcPhases    3352 drivers/gpu/drm/radeon/ci_dpm.c 		pi->smc_state_table.MemoryLevel[1].MinVddcPhases =
MinVddcPhases    3353 drivers/gpu/drm/radeon/ci_dpm.c 			pi->smc_state_table.MemoryLevel[0].MinVddcPhases;
MinVddcPhases     107 drivers/gpu/drm/radeon/smu7_discrete.h     uint32_t    MinVddcPhases;
MinVddcPhases     138 drivers/gpu/drm/radeon/smu7_discrete.h     uint32_t    MinVddcPhases;
MinVddcPhases     171 drivers/gpu/drm/radeon/smu7_discrete.h     uint32_t    MinVddcPhases;
MinVddcPhases     245 drivers/gpu/drm/radeon/smu7_discrete.h     uint8_t  MinVddcPhases;