mm_boot_level_offset 2371 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	uint32_t mm_boot_level_offset, mm_boot_level_value;
mm_boot_level_offset 2379 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	mm_boot_level_offset = smu_data->smu7_data.dpm_table_start + offsetof(SMU73_Discrete_DpmTable,
mm_boot_level_offset 2381 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	mm_boot_level_offset /= 4;
mm_boot_level_offset 2382 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	mm_boot_level_offset *= 4;
mm_boot_level_offset 2384 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 			CGS_IND_REG__SMC, mm_boot_level_offset);
mm_boot_level_offset 2388 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 			CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
mm_boot_level_offset 2403 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	uint32_t mm_boot_level_offset, mm_boot_level_value;
mm_boot_level_offset 2414 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	mm_boot_level_offset = smu_data->smu7_data.dpm_table_start +
mm_boot_level_offset 2416 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	mm_boot_level_offset /= 4;
mm_boot_level_offset 2417 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	mm_boot_level_offset *= 4;
mm_boot_level_offset 2419 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 			CGS_IND_REG__SMC, mm_boot_level_offset);
mm_boot_level_offset 2423 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 			CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
mm_boot_level_offset 2180 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	uint32_t mm_boot_level_offset, mm_boot_level_value;
mm_boot_level_offset 2188 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	mm_boot_level_offset = smu_data->smu7_data.dpm_table_start + offsetof(SMU74_Discrete_DpmTable,
mm_boot_level_offset 2190 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	mm_boot_level_offset /= 4;
mm_boot_level_offset 2191 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	mm_boot_level_offset *= 4;
mm_boot_level_offset 2193 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 			CGS_IND_REG__SMC, mm_boot_level_offset);
mm_boot_level_offset 2197 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 			CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
mm_boot_level_offset 2212 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	uint32_t mm_boot_level_offset, mm_boot_level_value;
mm_boot_level_offset 2223 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	mm_boot_level_offset = smu_data->smu7_data.dpm_table_start +
mm_boot_level_offset 2225 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	mm_boot_level_offset /= 4;
mm_boot_level_offset 2226 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	mm_boot_level_offset *= 4;
mm_boot_level_offset 2228 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 			CGS_IND_REG__SMC, mm_boot_level_offset);
mm_boot_level_offset 2232 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 			CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
mm_boot_level_offset 2679 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	uint32_t mm_boot_level_offset, mm_boot_level_value;
mm_boot_level_offset 2687 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	mm_boot_level_offset = smu_data->smu7_data.dpm_table_start +
mm_boot_level_offset 2689 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	mm_boot_level_offset /= 4;
mm_boot_level_offset 2690 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	mm_boot_level_offset *= 4;
mm_boot_level_offset 2692 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 			CGS_IND_REG__SMC, mm_boot_level_offset);
mm_boot_level_offset 2697 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 				mm_boot_level_offset, mm_boot_level_value);
mm_boot_level_offset 2713 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	uint32_t mm_boot_level_offset, mm_boot_level_value;
mm_boot_level_offset 2721 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	mm_boot_level_offset = smu_data->smu7_data.dpm_table_start +
mm_boot_level_offset 2723 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	mm_boot_level_offset /= 4;
mm_boot_level_offset 2724 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	mm_boot_level_offset *= 4;
mm_boot_level_offset 2726 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 			CGS_IND_REG__SMC, mm_boot_level_offset);
mm_boot_level_offset 2730 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 			CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
mm_boot_level_offset  334 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	uint32_t mm_boot_level_offset, mm_boot_level_value;
mm_boot_level_offset  342 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	mm_boot_level_offset = smu_data->smu7_data.dpm_table_start + offsetof(SMU75_Discrete_DpmTable,
mm_boot_level_offset  344 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	mm_boot_level_offset /= 4;
mm_boot_level_offset  345 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	mm_boot_level_offset *= 4;
mm_boot_level_offset  347 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 			CGS_IND_REG__SMC, mm_boot_level_offset);
mm_boot_level_offset  351 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 			CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
mm_boot_level_offset  366 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	uint32_t mm_boot_level_offset, mm_boot_level_value;
mm_boot_level_offset  377 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	mm_boot_level_offset = smu_data->smu7_data.dpm_table_start +
mm_boot_level_offset  379 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	mm_boot_level_offset /= 4;
mm_boot_level_offset  380 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	mm_boot_level_offset *= 4;
mm_boot_level_offset  382 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 			CGS_IND_REG__SMC, mm_boot_level_offset);
mm_boot_level_offset  386 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 			CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);