Mhz 185 drivers/gpu/drm/amd/display/dc/dm_pp_smu.h enum pp_smu_status (*set_hard_min_dcfclk_by_freq)(struct pp_smu *pp, int Mhz); Mhz 191 drivers/gpu/drm/amd/display/dc/dm_pp_smu.h enum pp_smu_status (*set_min_deep_sleep_dcfclk)(struct pp_smu *pp, int Mhz); Mhz 196 drivers/gpu/drm/amd/display/dc/dm_pp_smu.h enum pp_smu_status (*set_hard_min_uclk_by_freq)(struct pp_smu *pp, int Mhz); Mhz 201 drivers/gpu/drm/amd/display/dc/dm_pp_smu.h enum pp_smu_status (*set_hard_min_socclk_by_freq)(struct pp_smu *pp, int Mhz); Mhz 210 drivers/gpu/drm/amd/display/dc/dm_pp_smu.h enum pp_smu_nv_clock_id clock_id, int Mhz);