mixer_op_mode     174 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c 				mixer[lm_idx].mixer_op_mode = 0;
mixer_op_mode     176 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c 				mixer[lm_idx].mixer_op_mode |=
mixer_op_mode     204 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c 		mixer[i].mixer_op_mode = 0;
mixer_op_mode     220 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c 		lm->ops.setup_alpha_out(lm, mixer[i].mixer_op_mode);
mixer_op_mode     230 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c 			mixer[i].mixer_op_mode,
mixer_op_mode      82 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h 	u32 mixer_op_mode;
mixer_op_mode     137 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c 	uint32_t mixer_op_mode)
mixer_op_mode     145 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c 	op_mode = (op_mode & (BIT(31) | BIT(30))) | mixer_op_mode;
mixer_op_mode     231 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c 	u32 mixer_op_mode = 0;
mixer_op_mode     299 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c 			mixer_op_mode = 0;
mixer_op_mode     301 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c 			mixer_op_mode |= mdp5_lm_use_fg_alpha_mask(i);
mixer_op_mode     349 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c 		   val | mixer_op_mode);
mixer_op_mode     353 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c 			   val | mixer_op_mode);