mix_ctl 515 drivers/net/ethernet/cavium/octeon/octeon_mgmt.c union cvmx_mixx_ctl mix_ctl; mix_ctl 519 drivers/net/ethernet/cavium/octeon/octeon_mgmt.c mix_ctl.u64 = 0; mix_ctl 520 drivers/net/ethernet/cavium/octeon/octeon_mgmt.c cvmx_write_csr(p->mix + MIX_CTL, mix_ctl.u64); mix_ctl 522 drivers/net/ethernet/cavium/octeon/octeon_mgmt.c mix_ctl.u64 = cvmx_read_csr(p->mix + MIX_CTL); mix_ctl 523 drivers/net/ethernet/cavium/octeon/octeon_mgmt.c } while (mix_ctl.s.busy); mix_ctl 524 drivers/net/ethernet/cavium/octeon/octeon_mgmt.c mix_ctl.s.reset = 1; mix_ctl 525 drivers/net/ethernet/cavium/octeon/octeon_mgmt.c cvmx_write_csr(p->mix + MIX_CTL, mix_ctl.u64); mix_ctl 970 drivers/net/ethernet/cavium/octeon/octeon_mgmt.c union cvmx_mixx_ctl mix_ctl; mix_ctl 1009 drivers/net/ethernet/cavium/octeon/octeon_mgmt.c mix_ctl.u64 = cvmx_read_csr(p->mix + MIX_CTL); mix_ctl 1012 drivers/net/ethernet/cavium/octeon/octeon_mgmt.c if (mix_ctl.s.reset) { mix_ctl 1013 drivers/net/ethernet/cavium/octeon/octeon_mgmt.c mix_ctl.s.reset = 0; mix_ctl 1014 drivers/net/ethernet/cavium/octeon/octeon_mgmt.c cvmx_write_csr(p->mix + MIX_CTL, mix_ctl.u64); mix_ctl 1016 drivers/net/ethernet/cavium/octeon/octeon_mgmt.c mix_ctl.u64 = cvmx_read_csr(p->mix + MIX_CTL); mix_ctl 1017 drivers/net/ethernet/cavium/octeon/octeon_mgmt.c } while (mix_ctl.s.reset); mix_ctl 1063 drivers/net/ethernet/cavium/octeon/octeon_mgmt.c mix_ctl.u64 = 0; mix_ctl 1064 drivers/net/ethernet/cavium/octeon/octeon_mgmt.c mix_ctl.s.crc_strip = 1; /* Strip the ending CRC */ mix_ctl 1065 drivers/net/ethernet/cavium/octeon/octeon_mgmt.c mix_ctl.s.en = 1; /* Enable the port */ mix_ctl 1066 drivers/net/ethernet/cavium/octeon/octeon_mgmt.c mix_ctl.s.nbtarb = 0; /* Arbitration mode */ mix_ctl 1068 drivers/net/ethernet/cavium/octeon/octeon_mgmt.c mix_ctl.s.mrq_hwm = 1; mix_ctl 1070 drivers/net/ethernet/cavium/octeon/octeon_mgmt.c mix_ctl.s.lendian = 1; mix_ctl 1072 drivers/net/ethernet/cavium/octeon/octeon_mgmt.c cvmx_write_csr(p->mix + MIX_CTL, mix_ctl.u64);