misc_mask          38 arch/powerpc/platforms/512x/mpc5121_ads_cpld.c 	u8 misc_mask;
misc_mask          48 arch/powerpc/platforms/512x/mpc5121_ads_cpld.c 	return irq <= 7 ? &cpld_regs->pci_mask : &cpld_regs->misc_mask;
misc_mask         115 arch/powerpc/platforms/512x/mpc5121_ads_cpld.c 		&cpld_regs->misc_mask);
misc_mask         187 arch/powerpc/platforms/512x/mpc5121_ads_cpld.c 	out_8(&cpld_regs->misc_mask, ~(MISC_IGNORE));
misc_mask        1277 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c 	struct mlx5dr_match_misc *misc_mask = &value->misc;
misc_mask        1293 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c 		if (misc_mask->inner_second_cvlan_tag ||
misc_mask        1294 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c 		    misc_mask->inner_second_svlan_tag) {
misc_mask        1296 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c 			misc_mask->inner_second_cvlan_tag = 0;
misc_mask        1297 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c 			misc_mask->inner_second_svlan_tag = 0;
misc_mask        1301 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c 				  second_vlan_id, misc_mask, inner_second_vid);
misc_mask        1303 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c 				  second_cfi, misc_mask, inner_second_cfi);
misc_mask        1305 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c 				  second_priority, misc_mask, inner_second_prio);
misc_mask        1307 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c 		if (misc_mask->outer_second_cvlan_tag ||
misc_mask        1308 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c 		    misc_mask->outer_second_svlan_tag) {
misc_mask        1310 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c 			misc_mask->outer_second_cvlan_tag = 0;
misc_mask        1311 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c 			misc_mask->outer_second_svlan_tag = 0;
misc_mask        1315 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c 				  second_vlan_id, misc_mask, outer_second_vid);
misc_mask        1317 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c 				  second_cfi, misc_mask, outer_second_cfi);
misc_mask        1319 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c 				  second_priority, misc_mask, outer_second_prio);
misc_mask        1699 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c 	struct mlx5dr_match_misc *misc_mask = &value->misc;
misc_mask        1701 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c 	DR_STE_SET_MASK_V(gre, bit_mask, gre_protocol, misc_mask, gre_protocol);
misc_mask        1702 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c 	DR_STE_SET_MASK_V(gre, bit_mask, gre_k_present, misc_mask, gre_k_present);
misc_mask        1703 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c 	DR_STE_SET_MASK_V(gre, bit_mask, gre_key_h, misc_mask, gre_key_h);
misc_mask        1704 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c 	DR_STE_SET_MASK_V(gre, bit_mask, gre_key_l, misc_mask, gre_key_l);
misc_mask        1706 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c 	DR_STE_SET_MASK_V(gre, bit_mask, gre_c_present, misc_mask, gre_c_present);
misc_mask        1707 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c 	DR_STE_SET_MASK_V(gre, bit_mask, gre_s_present, misc_mask, gre_s_present);
misc_mask        2233 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c 	struct mlx5dr_match_misc *misc_mask = &value->misc;
misc_mask        2236 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c 	if (misc_mask->source_port && misc_mask->source_port != 0xffff)
misc_mask        2240 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c 	if (misc_mask->source_eswitch_owner_vhca_id &&
misc_mask        2241 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c 	    misc_mask->source_eswitch_owner_vhca_id != 0xffff)
misc_mask        2244 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c 	DR_STE_SET_MASK(src_gvmi_qp, bit_mask, source_gvmi, misc_mask, source_port);
misc_mask        2245 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c 	DR_STE_SET_MASK(src_gvmi_qp, bit_mask, source_qp, misc_mask, source_sqn);
misc_mask        2246 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c 	misc_mask->source_eswitch_owner_vhca_id = 0;