mis               590 arch/x86/events/intel/lbr.c 		u64 from, to, mis = 0, pred = 0, in_tx = 0, abort = 0;
mis               609 arch/x86/events/intel/lbr.c 			mis = !!(info & LBR_INFO_MISPRED);
mis               610 arch/x86/events/intel/lbr.c 			pred = !mis;
mis               617 arch/x86/events/intel/lbr.c 			mis = !!(from & LBR_FROM_FLAG_MISPRED);
mis               618 arch/x86/events/intel/lbr.c 			pred = !mis;
mis               626 arch/x86/events/intel/lbr.c 			mis = !!(from & LBR_FROM_FLAG_MISPRED);
mis               627 arch/x86/events/intel/lbr.c 			pred = !mis;
mis               650 arch/x86/events/intel/lbr.c 		cpuc->lbr_entries[out].mispred	 = mis;
mis                44 drivers/crypto/ux500/cryp/cryp_irq.c 	return (readl_relaxed(&device_data->base->mis) & irq_src) > 0;
mis                92 drivers/crypto/ux500/cryp/cryp_irqp.h 	u32 mis;		/* Masked interrupt statu register  */
mis               523 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	secondary_pipe->plane_res.mi = pool->mis[secondary_pipe->pipe_idx];
mis              1617 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 			pipe_ctx->plane_res.mi = pool->mis[i];
mis              1887 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 		pipe_ctx->plane_res.mi = pool->mis[tg_inst];
mis               696 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c 		if (pool->base.mis[i] != NULL) {
mis               697 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c 			kfree(TO_DCE_MEM_INPUT(pool->base.mis[i]));
mis               698 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c 			pool->base.mis[i] = NULL;
mis              1012 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c 		pool->base.mis[i] = dce100_mem_input_create(ctx, i);
mis              1013 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c 		if (pool->base.mis[i] == NULL) {
mis               753 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c 		if (pool->base.mis[i] != NULL) {
mis               754 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c 			kfree(TO_DCE_MEM_INPUT(pool->base.mis[i]));
mis               755 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c 			pool->base.mis[i] = NULL;
mis              1062 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c 	pipe_ctx->plane_res.mi = pool->mis[underlay_idx];
mis              1194 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c 	pool->mis[pool->pipe_count] = &dce110_miv->base;
mis              1370 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c 		pool->base.mis[i] = dce110_mem_input_create(ctx, i);
mis              1371 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c 		if (pool->base.mis[i] == NULL) {
mis               715 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c 		if (pool->base.mis[i] != NULL) {
mis               716 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c 			kfree(TO_DCE_MEM_INPUT(pool->base.mis[i]));
mis               717 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c 			pool->base.mis[i] = NULL;
mis              1257 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c 		pool->base.mis[i] = dce112_mem_input_create(ctx, i);
mis              1258 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c 		if (pool->base.mis[i] == NULL) {
mis               562 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c 		if (pool->base.mis[i] != NULL) {
mis               563 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c 			kfree(TO_DCE_MEM_INPUT(pool->base.mis[i]));
mis               564 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c 			pool->base.mis[i] = NULL;
mis              1106 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c 		pool->base.mis[j] = dce120_mem_input_create(ctx, i);
mis              1108 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c 		if (pool->base.mis[j] == NULL) {
mis               744 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c 		if (pool->base.mis[i] != NULL) {
mis               745 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c 			kfree(TO_DCE_MEM_INPUT(pool->base.mis[i]));
mis               746 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c 			pool->base.mis[i] = NULL;
mis               979 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c 		pool->base.mis[i] = dce80_mem_input_create(ctx, i);
mis               980 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c 		if (pool->base.mis[i] == NULL) {
mis              1176 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c 		pool->base.mis[i] = dce80_mem_input_create(ctx, i);
mis              1177 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c 		if (pool->base.mis[i] == NULL) {
mis              1369 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c 		pool->base.mis[i] = dce80_mem_input_create(ctx, i);
mis              1370 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c 		if (pool->base.mis[i] == NULL) {
mis              1733 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	next_odm_pipe->plane_res.mi = pool->mis[next_odm_pipe->pipe_idx];
mis              1813 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	secondary_pipe->plane_res.mi = pool->mis[secondary_pipe->pipe_idx];
mis               165 drivers/gpu/drm/amd/display/dc/inc/core_types.h 	struct mem_input *mis[MAX_PIPES];
mis              1544 drivers/media/dvb-frontends/stv0900_core.c 				enum fe_stv0900_demod_num demod, int mis)
mis              1548 drivers/media/dvb-frontends/stv0900_core.c 	if (mis < 0 || mis > 255) {
mis              1552 drivers/media/dvb-frontends/stv0900_core.c 		dprintk("Enable MIS filtering - %d\n", mis);
mis              1554 drivers/media/dvb-frontends/stv0900_core.c 		stv0900_write_reg(intp, ISIENTRY, mis);
mis              3436 drivers/media/dvb-frontends/stv090x.c static int stv090x_set_mis(struct stv090x_state *state, int mis)
mis              3440 drivers/media/dvb-frontends/stv090x.c 	if (mis < 0 || mis > 255) {
mis              3447 drivers/media/dvb-frontends/stv090x.c 		dprintk(FE_DEBUG, 1, "Enable MIS filtering - %d", mis);
mis              3452 drivers/media/dvb-frontends/stv090x.c 		if (STV090x_WRITE_DEMOD(state, ISIENTRY, mis) < 0)
mis                47 drivers/pinctrl/spear/pinctrl-plgpio.c 	u32 mis;		/* mask interrupt status register */
mis               373 drivers/pinctrl/spear/pinctrl-plgpio.c 		pending = readl_relaxed(plgpio->base + plgpio->regs.mis +
mis               379 drivers/pinctrl/spear/pinctrl-plgpio.c 		writel_relaxed(~pending, plgpio->base + plgpio->regs.mis +
mis               499 drivers/pinctrl/spear/pinctrl-plgpio.c 		plgpio->regs.mis = val;