mipi_mmio_base   1830 drivers/gpu/drm/i915/display/vlv_dsi.c 		dev_priv->mipi_mmio_base = BXT_MIPI_BASE;
mipi_mmio_base   1832 drivers/gpu/drm/i915/display/vlv_dsi.c 		dev_priv->mipi_mmio_base = VLV_MIPI_BASE;
mipi_mmio_base   1337 drivers/gpu/drm/i915/i915_drv.h 	u32 mipi_mmio_base;
mipi_mmio_base   10580 drivers/gpu/drm/i915/i915_reg.h #define _MIPIA_DEVICE_READY		(dev_priv->mipi_mmio_base + 0xb000)
mipi_mmio_base   10581 drivers/gpu/drm/i915/i915_reg.h #define _MIPIC_DEVICE_READY		(dev_priv->mipi_mmio_base + 0xb800)
mipi_mmio_base   10590 drivers/gpu/drm/i915/i915_reg.h #define _MIPIA_INTR_STAT		(dev_priv->mipi_mmio_base + 0xb004)
mipi_mmio_base   10591 drivers/gpu/drm/i915/i915_reg.h #define _MIPIC_INTR_STAT		(dev_priv->mipi_mmio_base + 0xb804)
mipi_mmio_base   10593 drivers/gpu/drm/i915/i915_reg.h #define _MIPIA_INTR_EN			(dev_priv->mipi_mmio_base + 0xb008)
mipi_mmio_base   10594 drivers/gpu/drm/i915/i915_reg.h #define _MIPIC_INTR_EN			(dev_priv->mipi_mmio_base + 0xb808)
mipi_mmio_base   10629 drivers/gpu/drm/i915/i915_reg.h #define _MIPIA_DSI_FUNC_PRG		(dev_priv->mipi_mmio_base + 0xb00c)
mipi_mmio_base   10630 drivers/gpu/drm/i915/i915_reg.h #define _MIPIC_DSI_FUNC_PRG		(dev_priv->mipi_mmio_base + 0xb80c)
mipi_mmio_base   10652 drivers/gpu/drm/i915/i915_reg.h #define _MIPIA_HS_TX_TIMEOUT		(dev_priv->mipi_mmio_base + 0xb010)
mipi_mmio_base   10653 drivers/gpu/drm/i915/i915_reg.h #define _MIPIC_HS_TX_TIMEOUT		(dev_priv->mipi_mmio_base + 0xb810)
mipi_mmio_base   10657 drivers/gpu/drm/i915/i915_reg.h #define _MIPIA_LP_RX_TIMEOUT		(dev_priv->mipi_mmio_base + 0xb014)
mipi_mmio_base   10658 drivers/gpu/drm/i915/i915_reg.h #define _MIPIC_LP_RX_TIMEOUT		(dev_priv->mipi_mmio_base + 0xb814)
mipi_mmio_base   10662 drivers/gpu/drm/i915/i915_reg.h #define _MIPIA_TURN_AROUND_TIMEOUT	(dev_priv->mipi_mmio_base + 0xb018)
mipi_mmio_base   10663 drivers/gpu/drm/i915/i915_reg.h #define _MIPIC_TURN_AROUND_TIMEOUT	(dev_priv->mipi_mmio_base + 0xb818)
mipi_mmio_base   10667 drivers/gpu/drm/i915/i915_reg.h #define _MIPIA_DEVICE_RESET_TIMER	(dev_priv->mipi_mmio_base + 0xb01c)
mipi_mmio_base   10668 drivers/gpu/drm/i915/i915_reg.h #define _MIPIC_DEVICE_RESET_TIMER	(dev_priv->mipi_mmio_base + 0xb81c)
mipi_mmio_base   10672 drivers/gpu/drm/i915/i915_reg.h #define _MIPIA_DPI_RESOLUTION		(dev_priv->mipi_mmio_base + 0xb020)
mipi_mmio_base   10673 drivers/gpu/drm/i915/i915_reg.h #define _MIPIC_DPI_RESOLUTION		(dev_priv->mipi_mmio_base + 0xb820)
mipi_mmio_base   10680 drivers/gpu/drm/i915/i915_reg.h #define _MIPIA_DBI_FIFO_THROTTLE	(dev_priv->mipi_mmio_base + 0xb024)
mipi_mmio_base   10681 drivers/gpu/drm/i915/i915_reg.h #define _MIPIC_DBI_FIFO_THROTTLE	(dev_priv->mipi_mmio_base + 0xb824)
mipi_mmio_base   10688 drivers/gpu/drm/i915/i915_reg.h #define _MIPIA_HSYNC_PADDING_COUNT	(dev_priv->mipi_mmio_base + 0xb028)
mipi_mmio_base   10689 drivers/gpu/drm/i915/i915_reg.h #define _MIPIC_HSYNC_PADDING_COUNT	(dev_priv->mipi_mmio_base + 0xb828)
mipi_mmio_base   10692 drivers/gpu/drm/i915/i915_reg.h #define _MIPIA_HBP_COUNT		(dev_priv->mipi_mmio_base + 0xb02c)
mipi_mmio_base   10693 drivers/gpu/drm/i915/i915_reg.h #define _MIPIC_HBP_COUNT		(dev_priv->mipi_mmio_base + 0xb82c)
mipi_mmio_base   10696 drivers/gpu/drm/i915/i915_reg.h #define _MIPIA_HFP_COUNT		(dev_priv->mipi_mmio_base + 0xb030)
mipi_mmio_base   10697 drivers/gpu/drm/i915/i915_reg.h #define _MIPIC_HFP_COUNT		(dev_priv->mipi_mmio_base + 0xb830)
mipi_mmio_base   10700 drivers/gpu/drm/i915/i915_reg.h #define _MIPIA_HACTIVE_AREA_COUNT	(dev_priv->mipi_mmio_base + 0xb034)
mipi_mmio_base   10701 drivers/gpu/drm/i915/i915_reg.h #define _MIPIC_HACTIVE_AREA_COUNT	(dev_priv->mipi_mmio_base + 0xb834)
mipi_mmio_base   10704 drivers/gpu/drm/i915/i915_reg.h #define _MIPIA_VSYNC_PADDING_COUNT	(dev_priv->mipi_mmio_base + 0xb038)
mipi_mmio_base   10705 drivers/gpu/drm/i915/i915_reg.h #define _MIPIC_VSYNC_PADDING_COUNT	(dev_priv->mipi_mmio_base + 0xb838)
mipi_mmio_base   10708 drivers/gpu/drm/i915/i915_reg.h #define _MIPIA_VBP_COUNT		(dev_priv->mipi_mmio_base + 0xb03c)
mipi_mmio_base   10709 drivers/gpu/drm/i915/i915_reg.h #define _MIPIC_VBP_COUNT		(dev_priv->mipi_mmio_base + 0xb83c)
mipi_mmio_base   10712 drivers/gpu/drm/i915/i915_reg.h #define _MIPIA_VFP_COUNT		(dev_priv->mipi_mmio_base + 0xb040)
mipi_mmio_base   10713 drivers/gpu/drm/i915/i915_reg.h #define _MIPIC_VFP_COUNT		(dev_priv->mipi_mmio_base + 0xb840)
mipi_mmio_base   10716 drivers/gpu/drm/i915/i915_reg.h #define _MIPIA_HIGH_LOW_SWITCH_COUNT	(dev_priv->mipi_mmio_base + 0xb044)
mipi_mmio_base   10717 drivers/gpu/drm/i915/i915_reg.h #define _MIPIC_HIGH_LOW_SWITCH_COUNT	(dev_priv->mipi_mmio_base + 0xb844)
mipi_mmio_base   10722 drivers/gpu/drm/i915/i915_reg.h #define _MIPIA_DPI_CONTROL		(dev_priv->mipi_mmio_base + 0xb048)
mipi_mmio_base   10723 drivers/gpu/drm/i915/i915_reg.h #define _MIPIC_DPI_CONTROL		(dev_priv->mipi_mmio_base + 0xb848)
mipi_mmio_base   10733 drivers/gpu/drm/i915/i915_reg.h #define _MIPIA_DPI_DATA			(dev_priv->mipi_mmio_base + 0xb04c)
mipi_mmio_base   10734 drivers/gpu/drm/i915/i915_reg.h #define _MIPIC_DPI_DATA			(dev_priv->mipi_mmio_base + 0xb84c)
mipi_mmio_base   10739 drivers/gpu/drm/i915/i915_reg.h #define _MIPIA_INIT_COUNT		(dev_priv->mipi_mmio_base + 0xb050)
mipi_mmio_base   10740 drivers/gpu/drm/i915/i915_reg.h #define _MIPIC_INIT_COUNT		(dev_priv->mipi_mmio_base + 0xb850)
mipi_mmio_base   10745 drivers/gpu/drm/i915/i915_reg.h #define _MIPIA_MAX_RETURN_PKT_SIZE	(dev_priv->mipi_mmio_base + 0xb054)
mipi_mmio_base   10746 drivers/gpu/drm/i915/i915_reg.h #define _MIPIC_MAX_RETURN_PKT_SIZE	(dev_priv->mipi_mmio_base + 0xb854)
mipi_mmio_base   10752 drivers/gpu/drm/i915/i915_reg.h #define _MIPIA_VIDEO_MODE_FORMAT	(dev_priv->mipi_mmio_base + 0xb058)
mipi_mmio_base   10753 drivers/gpu/drm/i915/i915_reg.h #define _MIPIC_VIDEO_MODE_FORMAT	(dev_priv->mipi_mmio_base + 0xb858)
mipi_mmio_base   10762 drivers/gpu/drm/i915/i915_reg.h #define _MIPIA_EOT_DISABLE		(dev_priv->mipi_mmio_base + 0xb05c)
mipi_mmio_base   10763 drivers/gpu/drm/i915/i915_reg.h #define _MIPIC_EOT_DISABLE		(dev_priv->mipi_mmio_base + 0xb85c)
mipi_mmio_base   10776 drivers/gpu/drm/i915/i915_reg.h #define _MIPIA_LP_BYTECLK		(dev_priv->mipi_mmio_base + 0xb060)
mipi_mmio_base   10777 drivers/gpu/drm/i915/i915_reg.h #define _MIPIC_LP_BYTECLK		(dev_priv->mipi_mmio_base + 0xb860)
mipi_mmio_base   10782 drivers/gpu/drm/i915/i915_reg.h #define _MIPIA_TLPX_TIME_COUNT		(dev_priv->mipi_mmio_base + 0xb0a4)
mipi_mmio_base   10783 drivers/gpu/drm/i915/i915_reg.h #define _MIPIC_TLPX_TIME_COUNT		(dev_priv->mipi_mmio_base + 0xb8a4)
mipi_mmio_base   10786 drivers/gpu/drm/i915/i915_reg.h #define _MIPIA_CLK_LANE_TIMING		(dev_priv->mipi_mmio_base + 0xb098)
mipi_mmio_base   10787 drivers/gpu/drm/i915/i915_reg.h #define _MIPIC_CLK_LANE_TIMING		(dev_priv->mipi_mmio_base + 0xb898)
mipi_mmio_base   10791 drivers/gpu/drm/i915/i915_reg.h #define _MIPIA_LP_GEN_DATA		(dev_priv->mipi_mmio_base + 0xb064)
mipi_mmio_base   10792 drivers/gpu/drm/i915/i915_reg.h #define _MIPIC_LP_GEN_DATA		(dev_priv->mipi_mmio_base + 0xb864)
mipi_mmio_base   10796 drivers/gpu/drm/i915/i915_reg.h #define _MIPIA_HS_GEN_DATA		(dev_priv->mipi_mmio_base + 0xb068)
mipi_mmio_base   10797 drivers/gpu/drm/i915/i915_reg.h #define _MIPIC_HS_GEN_DATA		(dev_priv->mipi_mmio_base + 0xb868)
mipi_mmio_base   10800 drivers/gpu/drm/i915/i915_reg.h #define _MIPIA_LP_GEN_CTRL		(dev_priv->mipi_mmio_base + 0xb06c)
mipi_mmio_base   10801 drivers/gpu/drm/i915/i915_reg.h #define _MIPIC_LP_GEN_CTRL		(dev_priv->mipi_mmio_base + 0xb86c)
mipi_mmio_base   10803 drivers/gpu/drm/i915/i915_reg.h #define _MIPIA_HS_GEN_CTRL		(dev_priv->mipi_mmio_base + 0xb070)
mipi_mmio_base   10804 drivers/gpu/drm/i915/i915_reg.h #define _MIPIC_HS_GEN_CTRL		(dev_priv->mipi_mmio_base + 0xb870)
mipi_mmio_base   10816 drivers/gpu/drm/i915/i915_reg.h #define _MIPIA_GEN_FIFO_STAT		(dev_priv->mipi_mmio_base + 0xb074)
mipi_mmio_base   10817 drivers/gpu/drm/i915/i915_reg.h #define _MIPIC_GEN_FIFO_STAT		(dev_priv->mipi_mmio_base + 0xb874)
mipi_mmio_base   10834 drivers/gpu/drm/i915/i915_reg.h #define _MIPIA_HS_LS_DBI_ENABLE		(dev_priv->mipi_mmio_base + 0xb078)
mipi_mmio_base   10835 drivers/gpu/drm/i915/i915_reg.h #define _MIPIC_HS_LS_DBI_ENABLE		(dev_priv->mipi_mmio_base + 0xb878)
mipi_mmio_base   10841 drivers/gpu/drm/i915/i915_reg.h #define _MIPIA_DPHY_PARAM		(dev_priv->mipi_mmio_base + 0xb080)
mipi_mmio_base   10842 drivers/gpu/drm/i915/i915_reg.h #define _MIPIC_DPHY_PARAM		(dev_priv->mipi_mmio_base + 0xb880)
mipi_mmio_base   11090 drivers/gpu/drm/i915/i915_reg.h #define _MIPIA_DBI_BW_CTRL		(dev_priv->mipi_mmio_base + 0xb084)
mipi_mmio_base   11091 drivers/gpu/drm/i915/i915_reg.h #define _MIPIC_DBI_BW_CTRL		(dev_priv->mipi_mmio_base + 0xb884)
mipi_mmio_base   11094 drivers/gpu/drm/i915/i915_reg.h #define _MIPIA_CLK_LANE_SWITCH_TIME_CNT		(dev_priv->mipi_mmio_base + 0xb088)
mipi_mmio_base   11095 drivers/gpu/drm/i915/i915_reg.h #define _MIPIC_CLK_LANE_SWITCH_TIME_CNT		(dev_priv->mipi_mmio_base + 0xb888)
mipi_mmio_base   11102 drivers/gpu/drm/i915/i915_reg.h #define _MIPIA_STOP_STATE_STALL		(dev_priv->mipi_mmio_base + 0xb08c)
mipi_mmio_base   11103 drivers/gpu/drm/i915/i915_reg.h #define _MIPIC_STOP_STATE_STALL		(dev_priv->mipi_mmio_base + 0xb88c)
mipi_mmio_base   11108 drivers/gpu/drm/i915/i915_reg.h #define _MIPIA_INTR_STAT_REG_1		(dev_priv->mipi_mmio_base + 0xb090)
mipi_mmio_base   11109 drivers/gpu/drm/i915/i915_reg.h #define _MIPIC_INTR_STAT_REG_1		(dev_priv->mipi_mmio_base + 0xb890)
mipi_mmio_base   11111 drivers/gpu/drm/i915/i915_reg.h #define _MIPIA_INTR_EN_REG_1		(dev_priv->mipi_mmio_base + 0xb094)
mipi_mmio_base   11112 drivers/gpu/drm/i915/i915_reg.h #define _MIPIC_INTR_EN_REG_1		(dev_priv->mipi_mmio_base + 0xb894)
mipi_mmio_base   11117 drivers/gpu/drm/i915/i915_reg.h #define MIPIA_DBI_TYPEC_CTRL		(dev_priv->mipi_mmio_base + 0xb100)
mipi_mmio_base   11131 drivers/gpu/drm/i915/i915_reg.h #define _MIPIA_CTRL			(dev_priv->mipi_mmio_base + 0xb104)
mipi_mmio_base   11132 drivers/gpu/drm/i915/i915_reg.h #define _MIPIC_CTRL			(dev_priv->mipi_mmio_base + 0xb904)
mipi_mmio_base   11164 drivers/gpu/drm/i915/i915_reg.h #define _MIPIA_DATA_ADDRESS		(dev_priv->mipi_mmio_base + 0xb108)
mipi_mmio_base   11165 drivers/gpu/drm/i915/i915_reg.h #define _MIPIC_DATA_ADDRESS		(dev_priv->mipi_mmio_base + 0xb908)
mipi_mmio_base   11171 drivers/gpu/drm/i915/i915_reg.h #define _MIPIA_DATA_LENGTH		(dev_priv->mipi_mmio_base + 0xb10c)
mipi_mmio_base   11172 drivers/gpu/drm/i915/i915_reg.h #define _MIPIC_DATA_LENGTH		(dev_priv->mipi_mmio_base + 0xb90c)
mipi_mmio_base   11177 drivers/gpu/drm/i915/i915_reg.h #define _MIPIA_COMMAND_ADDRESS		(dev_priv->mipi_mmio_base + 0xb110)
mipi_mmio_base   11178 drivers/gpu/drm/i915/i915_reg.h #define _MIPIC_COMMAND_ADDRESS		(dev_priv->mipi_mmio_base + 0xb910)
mipi_mmio_base   11186 drivers/gpu/drm/i915/i915_reg.h #define _MIPIA_COMMAND_LENGTH		(dev_priv->mipi_mmio_base + 0xb114)
mipi_mmio_base   11187 drivers/gpu/drm/i915/i915_reg.h #define _MIPIC_COMMAND_LENGTH		(dev_priv->mipi_mmio_base + 0xb914)
mipi_mmio_base   11192 drivers/gpu/drm/i915/i915_reg.h #define _MIPIA_READ_DATA_RETURN0	(dev_priv->mipi_mmio_base + 0xb118)
mipi_mmio_base   11193 drivers/gpu/drm/i915/i915_reg.h #define _MIPIC_READ_DATA_RETURN0	(dev_priv->mipi_mmio_base + 0xb918)
mipi_mmio_base   11196 drivers/gpu/drm/i915/i915_reg.h #define _MIPIA_READ_DATA_VALID		(dev_priv->mipi_mmio_base + 0xb138)
mipi_mmio_base   11197 drivers/gpu/drm/i915/i915_reg.h #define _MIPIC_READ_DATA_VALID		(dev_priv->mipi_mmio_base + 0xb938)